{"id":18646718,"url":"https://github.com/rinhizakura/riscv-emulator","last_synced_at":"2025-04-11T12:31:58.788Z","repository":{"id":63165437,"uuid":"333504087","full_name":"RinHizakura/riscv-emulator","owner":"RinHizakura","description":"A project for learning RISC-V architecture purpose","archived":false,"fork":false,"pushed_at":"2023-11-09T07:02:08.000Z","size":8990,"stargazers_count":24,"open_issues_count":0,"forks_count":2,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-03-25T14:05:41.196Z","etag":null,"topics":["c","emulator","riscv","riscv-emulator"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/RinHizakura.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-01-27T17:18:44.000Z","updated_at":"2025-01-16T00:01:58.000Z","dependencies_parsed_at":"2023-01-22T11:01:04.613Z","dependency_job_id":"37aa429b-c8d1-462d-a11f-9bb675266529","html_url":"https://github.com/RinHizakura/riscv-emulator","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RinHizakura%2Friscv-emulator","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RinHizakura%2Friscv-emulator/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RinHizakura%2Friscv-emulator/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RinHizakura%2Friscv-emulator/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/RinHizakura","download_url":"https://codeload.github.com/RinHizakura/riscv-emulator/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248401990,"owners_count":21097328,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["c","emulator","riscv","riscv-emulator"],"created_at":"2024-11-07T06:22:14.766Z","updated_at":"2025-04-11T12:31:56.116Z","avatar_url":"https://github.com/RinHizakura.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# riscv-emulator\n**(Note: This project is still on the process for completion!)**\n\nThe project is built to learn RISC-V architecture as the purpose for me. It mainly comes\nfrom [rvemu](https://github.com/d0iasm/rvemu), which is a RISC-V emulator with\nRust implementation. Also, some of the idea of CPU implementation is borrowed from\n[riscv_em](https://github.com/franzflasch/riscv_em).\n\nThe emulator now supports fully RV64I, M, Zicsr, and Zifencei instructions. Most of the RV64C\nand some RV64A instructions are also supported.\n\n## Build and Run\n\nTo build the emulator:\n```\n$ make\n```\n\nAlthough the instruction cache isn't an esstential component for our emulator, but it could\nhelp to speed it with the fast path to decode an instruction! Note that the best\nconfiguration for the number of cache set and cache way will require more experiment, now\nthey just simply set to 8 and 4. To build the emulator with I-cache:\n```\n$ make ICACHE=1\n```\n\nThe emulator is also validated to run [xv6-riscv](https://github.com/mit-pdos/xv6-riscv),\nwhich is a simple UNIX operating system. You can use the provided binary by the following\ncommand directly:\n\n```\n$ make run-xv6\n```\n\nWe also try to support running Linux on the emulator. Although it still need some work to boot\ncompletly. You can take a try with the following command.\n\n```\n$ make run-linux\n```\n\nIf you want to run your own binary, the binary file in raw or ELF format are both supported.\nThe emulator will check whether the input binary is under ELF format first, otherwise it will\ntake it as a raw binary. You should notice that the process of ELF parsing now could be\nnon-general and ugly, so feel free to report if you can't load your ELF binary! To load and\nrun your binary on the emulator:\n```\n$ ./build/emu --binary \u003cbinary\u003e [--rfsimg \u003croot filesystem image\u003e]\n```\n\n## Compliance Test\n\nThe [riscv-arch-test](https://github.com/riscv/riscv-arch-test) is applied to check if\nimplementing the specifications correctly. We can pass RV64I, RV64M,\nand RV64C(except cebreak) now.\n\nYou'll need `riscof` to run the test. The following command could be use to simply\ninstall it. Please take a look at [RISCOF document](https://riscof.readthedocs.io/en/stable/index.html)\nif you find any problem when installing it.\n```\n$ pip3 install git+https://github.com/riscv/riscof.git\n```\n\nAfter installing `riscof`, You can run the compliance test by the following command.\n```\n$ make run-compliance\n```\n\n## Instruction Unit Test\n\nThe [riscv-tests](https://github.com/riscv-software-src/riscv-tests) is also applied to check\nif implementing the specifications correctly. We can pass RV64UI, RV64UM, RV64UC and RV64UA\nnow. You can run the riscv-tests by the following command.\n\n```\n$ make run-riscv-tests\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frinhizakura%2Friscv-emulator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frinhizakura%2Friscv-emulator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frinhizakura%2Friscv-emulator/lists"}