{"id":13603953,"url":"https://github.com/riscv-software-src/riscv-isa-sim","last_synced_at":"2025-05-13T20:22:28.556Z","repository":{"id":37646469,"uuid":"2276287","full_name":"riscv-software-src/riscv-isa-sim","owner":"riscv-software-src","description":"Spike, a RISC-V ISA Simulator","archived":false,"fork":false,"pushed_at":"2025-04-24T00:38:15.000Z","size":7909,"stargazers_count":2662,"open_issues_count":342,"forks_count":922,"subscribers_count":134,"default_branch":"master","last_synced_at":"2025-04-24T01:28:58.232Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/riscv-software-src.png","metadata":{"files":{"readme":"README.md","changelog":"ChangeLog.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2011-08-26T20:00:24.000Z","updated_at":"2025-04-24T00:38:20.000Z","dependencies_parsed_at":"2023-10-20T22:50:30.926Z","dependency_job_id":"c19eb1e5-dfc3-41cd-9fb8-bdc6bba28bf0","html_url":"https://github.com/riscv-software-src/riscv-isa-sim","commit_stats":{"total_commits":2922,"total_committers":204,"mean_commits":"14.323529411764707","dds":0.811088295687885,"last_synced_commit":"88fc84ded155a9e01987c4dfb7a77800e69b232b"},"previous_names":["riscv/riscv-isa-sim"],"tags_count":3,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscv-software-src%2Friscv-isa-sim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscv-software-src%2Friscv-isa-sim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscv-software-src%2Friscv-isa-sim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscv-software-src%2Friscv-isa-sim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/riscv-software-src","download_url":"https://codeload.github.com/riscv-software-src/riscv-isa-sim/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":251311332,"owners_count":21569008,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T19:00:37.143Z","updated_at":"2025-04-28T12:00:16.571Z","avatar_url":"https://github.com/riscv-software-src.png","language":"C","funding_links":[],"categories":["C"],"sub_categories":[],"readme":"Spike RISC-V ISA Simulator\n============================\n\nAbout\n-------------\n\nSpike, the RISC-V ISA Simulator, implements a functional model of one or more\nRISC-V harts.  It is named after the golden spike used to celebrate the\ncompletion of the US transcontinental railway.\n\nSpike supports the following RISC-V ISA features:\n  - RV32I and RV64I base ISAs, v2.1\n  - RV32E and RV64E base ISAs, v1.9\n  - Zifencei extension, v2.0\n  - Zicsr extension, v2.0\n  - Zicntr extension, v2.0\n  - M extension, v2.0\n  - A extension, v2.1\n  - B extension, v1.0\n  - F extension, v2.2\n  - D extension, v2.2\n  - Q extension, v2.2\n  - C extension, v2.0\n  - Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh scalar cryptography extensions (Zk, Zkn, and Zks groups), v1.0\n  - Zkr virtual entropy source emulation, v1.0\n  - V extension, v1.0 (_requires a 64-bit host_)\n  - P extension, v0.9.2\n  - Zba extension, v1.0\n  - Zbb extension, v1.0\n  - Zbc extension, v1.0\n  - Zbs extension, v1.0\n  - Zfh and Zfhmin half-precision floating-point extensions, v1.0\n  - Zfinx extension, v1.0\n  - Zmmul integer multiplication extension, v1.0\n  - Zicbom, Zicbop, Zicboz cache-block maintenance extensions, v1.0\n  - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)\n  - Machine, Supervisor, and User modes, v1.11\n  - Hypervisor extension, v1.0\n  - Svnapot extension, v1.0\n  - Svpbmt extension, v1.0\n  - Svinval extension, v1.0\n  - Svadu extension, v1.0\n  - Svade extension, v1.0\n  - Sdext extension, v1.0-STABLE\n  - Sdtrig extension, v1.0-STABLE\n  - Smepmp extension v1.0\n  - Smstateen extension, v1.0\n  - Smdbltrp extension, v1.0\n  - Sscofpmf v0.5.2\n  - Ssdbltrp extension, v1.0\n  - Ssqosid extension, v1.0\n  - Zaamo extension, v1.0\n  - Zalrsc extension, v1.0\n  - Zabha extension, v1.0\n  - Zacas extension, v1.0\n  - Zawrs extension, v1.0\n  - Zicfiss extension, v1.0\n  - Zicfilp extension, v1.0\n  - Zca extension, v1.0\n  - Zcb extension, v1.0\n  - Zcf extension, v1.0\n  - Zcd extension, v1.0\n  - Zcmp extension, v1.0\n  - Zcmt extension, v1.0\n  - Zfbfmin extension, v0.6\n  - Zvfbfmin extension, v0.6\n  - Zvfbfwma extension, v0.6\n  - Zvbb extension, v1.0\n  - Zvbc extension, v1.0\n  - Zvkg extension, v1.0\n  - Zvkned extension, v1.0\n  - Zvknha, Zvknhb extension, v1.0\n  - Zvksed extension, v1.0\n  - Zvksh extension, v1.0\n  - Zvkt  extension, v1.0\n  - Zvkn, Zvknc, Zvkng extension, v1.0\n  - Zvks, Zvksc, Zvksg extension, v1.0 \n  - Zicond extension, v1.0\n  - Zilsd extension, v1.0\n  - Zclsd extension, v1.0\n\nVersioning and APIs\n-------------------\n\nProjects are versioned primarily to indicate when the API has been extended or\nrendered incompatible.  In that spirit, Spike aims to follow the\n[SemVer](https://semver.org/spec/v2.0.0.html) versioning scheme, in which\nmajor version numbers are incremented when backwards-incompatible API changes\nare made; minor version numbers are incremented when new APIs are added; and\npatch version numbers are incremented when bugs are fixed in\na backwards-compatible manner.\n\nSpike's principal public API is the RISC-V ISA.  _The C++ interface to Spike's\ninternals is **not** considered a public API at this time_, and\nbackwards-incompatible changes to this interface _will_ be made without\nincrementing the major version number.\n\nBuild Steps\n---------------\n\nWe assume that the RISCV environment variable is set to the RISC-V tools\ninstall path.\n\n    $ apt-get install device-tree-compiler libboost-regex-dev libboost-system-dev\n    $ mkdir build\n    $ cd build\n    $ ../configure --prefix=$RISCV\n    $ make\n    $ [sudo] make install\n\nIf your system uses the `yum` package manager, you can substitute\n`yum install dtc` for the first step.\n\nBuild Steps on OpenBSD\n----------------------\n\nInstall bash, gmake, dtc, and use clang.\n\n    $ pkg_add bash gmake dtc\n    $ exec bash\n    $ export CC=cc; export CXX=c++\n    $ mkdir build\n    $ cd build\n    $ ../configure --prefix=$RISCV\n    $ gmake\n    $ [doas] make install\n\nCompiling and Running a Simple C Program\n-------------------------------------------\n\nInstall spike (see Build Steps), riscv-gnu-toolchain, and riscv-pk.\n\nWrite a short C program and name it hello.c.  Then, compile it into a RISC-V\nELF binary named hello:\n\n    $ riscv64-unknown-elf-gcc -o hello hello.c\n\nNow you can simulate the program atop the proxy kernel:\n\n    $ spike pk hello\n\nSimulating a New Instruction\n------------------------------------\n\nAdding an instruction to the simulator requires two steps:\n\n  1.  Describe the instruction's functional behavior in the file\n      riscv/insns/\u003cnew_instruction_name\u003e.h.  Examine other instructions\n      in that directory as a starting point.\n\n  2.  Add the opcode and opcode mask to riscv/opcodes.h.  Alternatively,\n      add it to the riscv-opcodes package, and it will do so for you:\n        ```\n         $ cd ../riscv-opcodes\n         $ vi opcodes       // add a line for the new instruction\n         $ make install\n        ```\n\n  3.  Add the instruction to riscv/riscv.mk.in. Otherwise, the instruction\n      will not be included in the build and will be treated as an illegal instruction.\n\n  4.  Rebuild the simulator.\n\nInteractive Debug Mode\n---------------------------\n\nTo invoke interactive debug mode, launch spike with -d:\n\n    $ spike -d pk hello\n\nTo see the contents of an integer register (0 is for core 0):\n\n    : reg 0 a0\n\nTo see the contents of a floating point register:\n\n    : fregs 0 ft0\n\nor:\n\n    : fregd 0 ft0\n\ndepending upon whether you wish to print the register as single- or double-precision.\n\nTo see the contents of a memory location (physical address in hex):\n\n    : mem 2020\n\nTo see the contents of memory with a virtual address (0 for core 0):\n\n    : mem 0 2020\n\nYou can advance by one instruction by pressing the enter key. You can also\nexecute until a desired equality is reached:\n\n    : until pc 0 2020                   (stop when pc=2020)\n    : until reg 0 mie a                 (stop when register mie=0xa)\n    : until mem 2020 50a9907311096993   (stop when mem[2020]=50a9907311096993)\n\nAlternatively, you can execute as long as an equality is true:\n\n    : while mem 2020 50a9907311096993\n\nYou can continue execution indefinitely by:\n\n    : r\n\nAt any point during execution (even without -d), you can enter the\ninteractive debug mode with `\u003ccontrol\u003e-\u003cc\u003e`.\n\nTo end the simulation from the debug prompt, press `\u003ccontrol\u003e-\u003cc\u003e` or:\n\n    : q\n\nDebugging With Gdb\n------------------\n\nAn alternative to interactive debug mode is to attach using gdb. Because spike\ntries to be like real hardware, you also need OpenOCD to do that. OpenOCD\ndoesn't currently know about address translation, so it's not possible to\neasily debug programs that are run under `pk`. We'll use the following test\nprogram:\n```\n$ cat rot13.c \nchar text[] = \"Vafgehpgvba frgf jnag gb or serr!\";\n\n// Don't use the stack, because sp isn't set up.\nvolatile int wait = 1;\n\nint main()\n{\n    while (wait)\n        ;\n\n    // Doesn't actually go on the stack, because there are lots of GPRs.\n    int i = 0;\n    while (text[i]) {\n        char lower = text[i] | 32;\n        if (lower \u003e= 'a' \u0026\u0026 lower \u003c= 'm')\n            text[i] += 13;\n        else if (lower \u003e 'm' \u0026\u0026 lower \u003c= 'z')\n            text[i] -= 13;\n        i++;\n    }\n\ndone:\n    while (!wait)\n        ;\n}\n$ cat spike.lds \nOUTPUT_ARCH( \"riscv\" )\n\nSECTIONS\n{\n  . = 0x10110000;\n  .text : { *(.text) }\n  .data : { *(.data) }\n}\n$ riscv64-unknown-elf-gcc -g -Og -o rot13-64.o -c rot13.c\n$ riscv64-unknown-elf-gcc -g -Og -T spike.lds -nostartfiles -o rot13-64 rot13-64.o\n```\n\nTo debug this program, first run spike telling it to listen for OpenOCD:\n```\n$ spike --rbb-port=9824 -m0x10100000:0x20000 rot13-64\nListening for remote bitbang connection on port 9824.\n```\n\nIn a separate shell run OpenOCD with the appropriate configuration file:\n```\n$ cat spike.cfg \nadapter driver remote_bitbang\nremote_bitbang host localhost\nremote_bitbang port 9824\n\nset _CHIPNAME riscv\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME riscv -chain-position $_TARGETNAME\n\ngdb_report_data_abort enable\n\ninit\nhalt\n$ openocd -f spike.cfg\nOpen On-Chip Debugger 0.10.0-dev-00002-gc3b344d (2017-06-08-12:14)\n...\nriscv.cpu: target state: halted\n```\n\nIn yet another shell, start your gdb debug session:\n```\ntnewsome@compy-vm:~/SiFive/spike-test$ riscv64-unknown-elf-gdb rot13-64\nGNU gdb (GDB) 8.0.50.20170724-git\nCopyright (C) 2017 Free Software Foundation, Inc.\nLicense GPLv3+: GNU GPL version 3 or later \u003chttp://gnu.org/licenses/gpl.html\u003e\nThis is free software: you are free to change and redistribute it.\nThere is NO WARRANTY, to the extent permitted by law.  Type \"show copying\"\nand \"show warranty\" for details.\nThis GDB was configured as \"--host=x86_64-pc-linux-gnu --target=riscv64-unknown-elf\".\nType \"show configuration\" for configuration details.\nFor bug reporting instructions, please see:\n\u003chttp://www.gnu.org/software/gdb/bugs/\u003e.\nFind the GDB manual and other documentation resources online at:\n\u003chttp://www.gnu.org/software/gdb/documentation/\u003e.\nFor help, type \"help\".\nType \"apropos word\" to search for commands related to \"word\"...\nReading symbols from rot13-64...done.\n(gdb) target remote localhost:3333\nRemote debugging using localhost:3333\n0x0000000010010004 in main () at rot13.c:8\n8\t    while (wait)\n(gdb) print wait\n$1 = 1\n(gdb) print wait=0\n$2 = 0\n(gdb) print text\n$3 = \"Vafgehpgvba frgf jnag gb or serr!\"\n(gdb) b done \nBreakpoint 1 at 0x10110064: file rot13.c, line 22.\n(gdb) c\nContinuing.\nDisabling abstract command writes to CSRs.\n\nBreakpoint 1, main () at rot13.c:23\n23\t    while (!wait)\n(gdb) print wait\n$4 = 0\n(gdb) print text\n...\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Friscv-software-src%2Friscv-isa-sim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Friscv-software-src%2Friscv-isa-sim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Friscv-software-src%2Friscv-isa-sim/lists"}