{"id":13399164,"url":"https://github.com/riscv-software-src/riscv-tests","last_synced_at":"2025-05-14T12:08:13.148Z","repository":{"id":8208417,"uuid":"9642428","full_name":"riscv-software-src/riscv-tests","owner":"riscv-software-src","description":null,"archived":false,"fork":false,"pushed_at":"2025-04-10T22:33:11.000Z","size":2823,"stargazers_count":973,"open_issues_count":140,"forks_count":494,"subscribers_count":78,"default_branch":"master","last_synced_at":"2025-04-13T20:18:11.282Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":"ruanyf/jstutorial","license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/riscv-software-src.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2013-04-24T08:05:07.000Z","updated_at":"2025-04-11T15:20:06.000Z","dependencies_parsed_at":"2023-10-14T00:10:07.083Z","dependency_job_id":"58cb6ad4-8882-4894-bcf6-ccde33e48a0d","html_url":"https://github.com/riscv-software-src/riscv-tests","commit_stats":{"total_commits":800,"total_committers":79,"mean_commits":"10.126582278481013","dds":0.6074999999999999,"last_synced_commit":"654419c440f2c7b452129b0d63a21528d12e9a04"},"previous_names":["riscv/riscv-tests"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscv-software-src%2Friscv-tests","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscv-software-src%2Friscv-tests/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscv-software-src%2Friscv-tests/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscv-software-src%2Friscv-tests/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/riscv-software-src","download_url":"https://codeload.github.com/riscv-software-src/riscv-tests/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248774961,"owners_count":21159534,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-07-30T19:00:34.781Z","updated_at":"2025-04-13T20:18:33.663Z","avatar_url":"https://github.com/riscv-software-src.png","language":"C","funding_links":[],"categories":["RISCV.ORG","C","Assembly"],"sub_categories":[],"readme":"riscv-tests\n================\n\nAbout\n-----------\n\nThis repository hosts unit tests for RISC-V processors.\n\nBuilding from repository\n-----------------------------\n\nWe assume that the RISCV environment variable is set to the RISC-V tools\ninstall path, and that the [riscv-gnu-toolchain](\nhttps://github.com/riscv-collab/riscv-gnu-toolchain) package is installed.\n\n    $ git clone https://github.com/riscv/riscv-tests\n    $ cd riscv-tests\n    $ git submodule update --init --recursive\n    $ autoconf\n    $ ./configure --prefix=$RISCV/target\n    $ make\n    $ make install\n\nThe rest of this document describes the format of test programs for the RISC-V\narchitecture.\n\nTest Virtual Machines\n-------------------------\n\nTo allow maximum reuse of a given test, each test program is constrained to\nonly use features of a given *test virtual machine* or TVM. A TVM hides\ndifferences between alternative implementations by defining:\n\n* The set of registers and instructions that can be used. \n* Which portions of memory can be accessed.\n* The way the test program starts and ends execution. \n* The way that test data is input.\n* The way that test results are output.\n\nThe following table shows the TVMs currently defined for RISC-V. All of these\nTVMs only support a single hardware thread.\n\nTVM Name | Description\n--- | ---\n`rv32ui` | RV32 user-level, integer only\n`rv32si` | RV32 supervisor-level, integer only\n`rv64ui` | RV64 user-level, integer only\n`rv64uf` | RV64 user-level, integer and floating-point\n`rv64uv` | RV64 user-level, integer, floating-point, and vector\n`rv64si` | RV64 supervisor-level, integer only\n`rv64sv` | RV64 supervisor-level, integer and vector\n\nA test program for RISC-V is written within a single assembly language file,\nwhich is passed through the C preprocessor, and all regular assembly\ndirectives can be used. An example test program is shown below. Each test\nprogram should first include the `riscv_test.h` header file, which defines the\nmacros used by the TVM. The header file will have different contents depending\non the target environment for which the test will be built.  One of the goals\nof the various TVMs is to allow the same test program to be compiled and run\non very different target environments yet still produce the same results. The\nfollowing table shows the target environment currently defined.\n\nTarget Environment Name | Description\n--- | ---\n`p` | virtual memory is disabled, only core 0 boots up\n`pm` | virtual memory is disabled, all cores boot up\n`pt` | virtual memory is disabled, timer interrupt fires every 100 cycles\n`v` | virtual memory is enabled\n\nEach test program must next specify for which TVM it is designed by including\nthe appropriate TVM macro, `RVTEST_RV64U` in this example. This specification\ncan change the way in which subsequent macros are interpreted, and supports\na static check of the TVM functionality used by the program.\n\nThe test program will begin execution at the first instruction after\n`RVTEST_CODE_BEGIN`, and continue until execution reaches an `RVTEST_PASS`\nmacro or the `RVTEST_CODE_END` macro, which is implicitly a success. A test\ncan explicitly fail by invoking the `RVTEST_FAIL` macro.\n\nThe example program contains self-checking code to test the result of the add.\nHowever, self-checks rely on correct functioning of the processor instructions\nused to implement the self check (e.g., the branch) and so cannot be the only\ntesting strategy.\n\nAll tests should also contain a test data section, delimited by\n`RVTEST_DATA_BEGIN` and `RVTEST_DATA_END`. There is no alignment guarantee for\nthe start of the test data section, so regular assembler alignment\ninstructions should be used to ensure desired alignment of data values. This\nregion of memory will be captured at the end of the test to act as a signature\nfrom the test. The signature can be compared with that from a run on the\ngolden model.\n\nAny given test environment for running tests should also include a timeout\nfacility, which will class a test as failing if it does not successfully\ncomplete a test within a reasonable time bound.\n\n    #include \"riscv_test.h\"\n\n    RVTEST_RV64U        # Define TVM used by program.\n\n    # Test code region.\n    RVTEST_CODE_BEGIN   # Start of test code.\n            lw      x2, testdata\n            addi    x2, 1         # Should be 42 into $2.\n            sw      x2, result    # Store result into memory overwriting 1s.\n            li      x3, 42        # Desired result.\n            bne     x2, x3, fail  # Fail out if doesn't match.\n            RVTEST_PASS           # Signal success.\n    fail:\n            RVTEST_FAIL\n    RVTEST_CODE_END     # End of test code.\n\n    # Input data section.\n    # This section is optional, and this data is NOT saved in the output.\n    .data\n            .align 3\n    testdata:\n            .dword 41\n\n    # Output data section.\n    RVTEST_DATA_BEGIN   # Start of test output data region.\n            .align 3\n    result:\n            .dword -1\n    RVTEST_DATA_END     # End of test output data region.\n\nUser-Level TVMs\n--------------------\n\nTest programs for the `rv32u*` and `rv64u*` TVMs can contain all instructions\nfrom the respective base user-level ISA (RV32 or RV64), except for those with\nthe SYSTEM major opcode (syscall, break, rdcycle, rdtime, rdinstret). All user\nregisters (pc, x0-x31, f0-f31, fsr) can be accessed.\n\nThe `rv32ui` and `rv64ui` TVMs are integer-only subsets of `rv32u` and `rv64u`\nrespectively. These subsets can not use any floating-point instructions (major\nopcodes: LOAD-FP, STORE-FP, MADD, MSUB, NMSUB, NMADD, OP-FP), and hence cannot\naccess the floating-point register state (f0-f31 and fsr). The integer-only\nTVMs are useful for initial processor bringup and to test simpler\nimplementations that lack a hardware FPU.\n\nNote that any `rv32ui` test program is also valid for the `rv32u` TVM, and\nsimilarly `rv64ui` is a strict subset of `rv64u`. To allow a given test to run\non the widest possible set of implementations, it is desirable to write any\ngiven test to run on the smallest or least capable TVM possible. For example,\nany simple tests of integer functionality should be written for the `rv64ui`\nTVM, as the same test can then be run on RV64 implementations with or without a\nhardware FPU. As another example, all tests for these base user-level TVMs will\nalso be valid for more advanced processors with instruction-set extensions.\n\nAt the start of execution, the values of all registers are undefined. All\nbranch and jump destinations must be to labels within the test code region of\nthe assembler source file. The code and data sections will be relocated\ndifferently for the various implementations of the test environment, and so\ntest program results shall not depend on absolute addresses of instructions or\ndata memory. The test build environment should support randomization of the\nsection relocation to provide better coverage and to ensure test signatures do\nnot contain absolute addresses.\n\nSupervisor-Level TVMs\n--------------------------\n\nThe supervisor-level TVMs allow testing of supervisor-level state and\ninstructions.  As with the user-level TVMs, we provide integer-only\nsupervisor-level TVMs indicated with a trailing `i`.\n\nHistory and Acknowledgements\n---------------------------------\n\nThis style of test virtual machine originated with the T0 (Torrent-0) vector\nmicroprocessor project at UC Berkeley and ICSI, begun in 1992. The main\ndevelopers of this test strategy were Krste Asanovic and David Johnson. A\nprecursor to `torture` was `rantor` developed by Phil Kohn at ICSI.\n\nA variant of this testing approach was also used for the Scale vector-thread\nprocessor at MIT, begun in 2000. Ronny Krashinsky and Christopher Batten were\nthe principal architects of the Scale chip. Jeffrey Cohen and Mark Hampton\ndeveloped a version of torture capable of generating vector-thread code.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Friscv-software-src%2Friscv-tests","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Friscv-software-src%2Friscv-tests","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Friscv-software-src%2Friscv-tests/lists"}