{"id":13647883,"url":"https://github.com/riscvarchive/riscv-cores-list","last_synced_at":"2025-04-22T06:32:14.102Z","repository":{"id":37810566,"uuid":"171934712","full_name":"riscvarchive/riscv-cores-list","owner":"riscvarchive","description":"RISC-V Cores, SoC platforms and SoCs","archived":true,"fork":false,"pushed_at":"2021-03-26T23:54:25.000Z","size":199,"stargazers_count":850,"open_issues_count":4,"forks_count":206,"subscribers_count":58,"default_branch":"master","last_synced_at":"2024-12-22T00:32:02.296Z","etag":null,"topics":["asic","fpga","open-isa","risc-v","socs"],"latest_commit_sha":null,"homepage":"https://riscv.org/risc-v-cores/","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/riscvarchive.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-02-21T19:47:14.000Z","updated_at":"2024-12-20T09:31:12.000Z","dependencies_parsed_at":"2022-08-08T22:01:20.604Z","dependency_job_id":null,"html_url":"https://github.com/riscvarchive/riscv-cores-list","commit_stats":null,"previous_names":["riscv/riscv-cores-list"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscvarchive%2Friscv-cores-list","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscvarchive%2Friscv-cores-list/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscvarchive%2Friscv-cores-list/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/riscvarchive%2Friscv-cores-list/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/riscvarchive","download_url":"https://codeload.github.com/riscvarchive/riscv-cores-list/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250183336,"owners_count":21388698,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","fpga","open-isa","risc-v","socs"],"created_at":"2024-08-02T01:03:49.170Z","updated_at":"2025-04-22T06:32:13.860Z","avatar_url":"https://github.com/riscvarchive.png","language":null,"funding_links":[],"categories":["Others"],"sub_categories":[],"readme":"# THIS PAGE IS NOW ARCHIVED - to make any additions or changes, please send email to content@riscv.org\n\n# RISC-V Cores and SoC Overview\n\nThis document captures the status of various cores and SoCs that endeavor to implement the RISC-V specification. Note that none of these cores/SoCs have passed the in-development RISC-V compliance suite.\n\nPlease add to the list and fix inaccuracies - see our [CONTRIBUTING file](https://github.com/riscv/riscv-cores-list/blob/master/CONTRIBUTING.md) for details.\n\n## Cores\n\nName | Supplier | Links | Capability | Priv. spec | User spec | Primary Language | License\n---- | -------- | ----- | ---------- | ---------- | --------- | ---------------- | -------\nAvispado  | SemiDynamics | [Website](https://semidynamics.com/products/avispado) | RV64 | 1.10 | RV64GC, 2.2, multicore, V-ready | SystemVerilog | Commercial License\nAtrevido  | SemiDynamics | [Website](https://semidynamics.com/products/atrevido) | RV64 | 1.10 | RV64GC, 2.2, multicore, V-ready | SystemVerilog | Commercial License\nRV32EC_P2 | IQonIC Works | [Website](http://iqonicworks.com/risc-v-ip/) | RV32 | 1.11 | RV32E[M]C/RV32I[M]C | SystemVerilog | IQonIC Works Commercial License\nRV32IC_P5 | IQonIC Works | [Website](http://iqonicworks.com/risc-v-ip/) | RV32 | 1.11 | RV32I[M][N][A]C | SystemVerilog | IQonIC Works Commercial License\nRV32EC_FMP5 | IQonIC Works | [Website](http://iqonicworks.com/risc-v-ip/) | RV32 | Custom | RV32EC | SystemVerilog | IQonIC Works Commercial License\nrocket | SiFive, UCB Bar| [GitHub](https://github.com/freechipsproject/rocket-chip) | RV32 | 1.11-draft | 2.3-draft | Chisel | BSD\nfreedom | SiFive | [GitHub](https://github.com/sifive/freedom) | RV32,RV64 | 1.11-draft | 2.3-draft | Chisel | BSD\nBerkeley Out-of-Order Machine (BOOM) | UCB BAR | [Website](https://boom-core.org/),[GitHub](https://github.com/riscv-boom/riscv-boom) | RV64 | 1.11-draft | 2.3-draft | Chisel | BSD\nCV32E40P | OpenHW Group | [GitHub](https://github.com/openhwgroup/cv32e40p) | RV32 | 1.11 | RV32IM[F]C | SystemVerilog | Solderpad Hardware License v. 0.51\nIbex (formerly Zero-riscy) | lowRISC | [GitHub](https://github.com/lowRISC/ibex) | RV32 | 1.11 | RV32I[M]C/RV32E[M]C | SystemVerilog | Apache 2.0\nCVA6 | OpenHW Group | [GitHub](https://github.com/openhwgroup/cva6) | RV32,RV64 | 1.11 | RV[32/64]GC | SystemVerilog | Solderpad Hardware License v. 0.51\nRiscy Processors | MIT CSAIL CSG | [Website](http://csg.csail.mit.edu/riscy-e/),[GitHub](https://github.com/csail-csg/riscy) | RV32,RV64 | | | Bluespec | MIT\nRiscyOO | MIT CSAIL CSG | [GitHub](https://github.com/csail-csg/riscy-OOO) | RV64 | 1.10 | RV64IMAFD | Bluespec | MIT\nLizard | Cornell CSL BRG | [GitHub](https://github.com/cornell-brg/lizard) | RV64 | | RV64IM | PyMTL | BSD\nMinerva | LambdaConcept | [GitHub](https://github.com/lambdaconcept/minerva) | RV32 | 1.10 | RV32I | nMigen | BSD\nOPenV/mriscv | OnChipUIS | [GitHub](https://github.com/onchipuis/mriscv) | RV32 | | RV32I(?) | Verilog | MIT\nVexRiscv | SpinalHDL | [GitHub](https://github.com/SpinalHDL/VexRiscv) | RV32 | 1.10 | RV32I/E[M][A][F[D]][C] | SpinalHDL | MIT\nVexRiscv Plugins for B and K | Romain Dolbeau | [GitHub](https://github.com/rdolbeau/VexRiscvBPluginGenerator/) | RV32 | N/A | RV32[B][K] for the VexRiscV core | SpinalHDL | MIT\nRoa Logic RV12 | Roa Logic | [GitHub](https://github.com/roalogic/RV12) | RV32 | 1.9.1 | 2.1 | SystemVerilog | Non-Commercial License\nSCR1 | Syntacore | [GitHub](https://github.com/syntacore/scr1) | RV32 | 1.10 | 2.2, RV32I/E[MC] | SystemVerilog | SHL v. 2.0\nSCR3 | Syntacore | [Website](https://syntacore.com/page/products/processor-ip/scr3) | RV32,RV64 | 1.10 | RV[32/64]IMC[A], 2.2, milticore | SystemVerilog | commercial\nSCR4 | Syntacore | [Website](https://syntacore.com/page/products/processor-ip/scr4) | RV32,RV64 | 1.10 | RV[32/64]IMCF[DA], 2.2, milticore | SystemVerilog | commercial\nSCR5 | Syntacore | [Website](https://syntacore.com/page/products/processor-ip/scr5) | RV32,RV64 | 1.10 | RV[32/64]IMC[FDA], 2.2, milticore | SystemVerilog | commercial\nSCR7 | Syntacore | [Website](https://syntacore.com/page/products/processor-ip/scr7) | RV64 | 1.10 | RV64GC, 2.2, milticore | SystemVerilog | commercial\nHummingbird E200 | Bob Hu | [GitHub](https://github.com/SI-RISCV/e200_opensource) | RV32 | 1.10 | 2.2, RV32IMAC | Verilog | Apache 2.0\nShakti | IIT Madras | [Website](http://shakti.org.in/),[GitLab](https://gitlab.com/shaktiproject) | RV64 | 1.11 | 2.2, RV64IMAFDC | Bluespec | BSD\nReonV | Lucas Castro | [GitHub](https://github.com/lcbcFoo/ReonV) | RV32 | | | VHDL | GPL v3\nPicoRV32 | Clifford Wolf | [GitHub](https://github.com/cliffordwolf/picorv32) | RV32 | | RV32I/E[MC] | Verilog | ISC\nMR1 | Tom Verbeure | [GitHub](https://github.com/tomverbeure/mr1) | RV32 | | RV32I | SpinalHDL | Unlicense\nSERV | Olof Kindgren | [GitHub](https://github.com/olofk/serv) | RV32 | | RV32I | Verilog | ISC\nSweRV EH1 | Western Digital Corporation | [GitHub](https://github.com/chipsalliance/Cores-SweRV) | RV32 | 1.11 | 2.1, RV32IMC | SystemVerilog | Apache 2.0\nSweRV EL2 | Western Digital Corporation | [GitHub](https://github.com/chipsalliance/Cores-SweRV-EL2) | RV32 | 1.11 | 2.1, RV32IMC | SystemVerilog | Apache 2.0\nSweRV EH2 | Western Digital Corporation | [GitHub](https://github.com/chipsalliance/Cores-SweRV-EH2) | RV32 | 1.11 | 2.1, RV32IMAC | SystemVerilog | Apache 2.0\nbiRISC-V | UltraEmbedded | [GitHub](https://github.com/ultraembedded/biriscv) | RV32 | 1.11 | RV32I[M] | Verilog | Apache 2.0\nReve-R | Gavin Stark | [GitHub](https://github.com/atthecodeface/cdl_hardware) | RV32 | 1.10 | RV32IMAC | CDL | Apache 2.0\nL10 | Codasip | [Website](https://codasip.com/risc-v-processors) | RV32 | 1.0 | RV32EMC | Verilog | Codasip EULA\nL30 | Codasip | [Website](https://codasip.com/risc-v-processors) | RV32 | 1.0 | RV32IMC | Verilog | Codasip EULA\nL30F | Codasip | [Website](https://codasip.com/risc-v-processors) | RV32 | 1.0 | RV32IMFC | Verilog | Codasip EULA\nL50 | Codasip | [Website](https://codasip.com/risc-v-processors) | RV32 | 1.0 | RV32IMC | Verilog | Codasip EULA\nL50F | Codasip | [Website](https://codasip.com/risc-v-processors) | RV32 | 1.0 | RV32IMFC | Verilog | Codasip EULA\nH50X | Codasip | [Website](https://codasip.com/risc-v-processors) | RV64 | 1.0 | RV64IMC | Verilog | Codasip EULA\nH50XF | Codasip | [Website](https://codasip.com/risc-v-processors) | RV64 | 1.0 | RV64IMFDC | Verilog | Codasip EULA\nA70X | Codasip | [Website](https://codasip.com/risc-v-processors) | RV64 | 1.0 | RV64IMAFDC | Verilog | Codasip EULA\nDarkRISCV | Darklife | [GitHub](https://github.com/darklife/darkriscv) | RV32 | | most of RV32I | Verilog | BSD\nRPU | Domipheus Labs | [GitHub](https://github.com/Domipheus/RPU) | RV32 | | RV32I | VHDL | Apache 2.0\nRV01 | Stefano Tonello | [OpenCores](https://opencores.org/projects/rv01_riscv_core) | RV32 | 1.7 | 2.1, RV32IM | VHDL | LPGL\nN22 | Andes | [Website](http://freestart.andestech.com/) | RV32 | 1.11 | RV32IMAC/EMAC + Andes V5/V5e ext. | Verilog | Andes FreeStart IPEA\nN25F | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-n25f/) | RV32 | 1.11 | RV32GC + Andes V5 ext. | Verilog | Andes Commercial License\nD25F | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-d25f/) | RV32 | 1.11 | RV32GCP + Andes V5 ext. | Verilog | Andes Commercial License\nA25 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-a25/) | RV32 | 1.11 | RV32GCP + Sv32 + Andes V5 ext. | Verilog | Andes Commercial License\nA25MP | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-a25mp/) | RV32 | 1.11 | RV32GCP + Sv32 + Andes V5 ext. + Multi-core | Verilog | Andes Commercial License\nNX25F | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx25f/) | RV64 | 1.11 | RV64GC + Andes V5 ext. | Verilog | Andes Commercial License\nAX25 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax25/) | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License\nAX25MP | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax25mp/) | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. + Multi-core | Verilog | Andes Commercial License\nA27 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-a27/) | RV32 | 1.11 | RV32GCP + Sv32 + Andes V5 ext. | Verilog | Andes Commercial License\nA27L2 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax27l2/) | RV32 | 1.11 | RV32GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License\nAX27 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax27/) | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License\nAX27L2 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax27l2/) | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License\nNX27V | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx27v/) | RV64 | 1.11 | RV64GCPV | Verilog | Andes Commercial License\nN45 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/) | RV32 | 1.11 | RV32GC + Andes V5 ext. | Verilog | Andes Commercial License\nD45 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-d45/) | RV32 | 1.11 | RV32GCP + Andes V5 ext. | Verilog | Andes Commercial License\nNX45 | Andes | [Website](http://whttp/www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/) | RV64 | 1.11 | RV64GC + Andes V5 ext. | Verilog | Andes Commercial License\nA45 | Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/) | RV32 | 1.11 | RV32GCP + Sv32 + Andes V5 ext. | Verilog | Andes Commercial License\nAX45| Andes | [Website](http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/) | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License\nInstant SoC | FPGA Cores | [Website](http://www.fpga-cores.com/instant-soc/) | RV32 |  | RV32IM | VHDL | Free Non Commercial\nTaiga | Reconfigurable Computing Lab, Simon Fraser University | [GitLab](https://gitlab.com/sfu-rcl/Taiga) | RV32 |  | RV32IMA | SystemVerilog | Apache 2.0\nMaestro | João Chrisóstomo | [GitHub](https://github.com/Artoriuz/maestro) | RV32 |  | RV32I | VHDL | MIT\nXuanTie C910 | T-Head (Alibaba group) | [Website](https://www.t-head.cn/product/c910?spm=a2ouz.12987052.0.0.5c5c6245WIbjoG) | RV64 | 1.10 |  RV64GCV + SV39 + ISA Extension + Memory model Extension + multi-core \u0026 multi-cluster(16 cores maximum) | Verilog | Alibaba commercial license\nXuanTie C906 | T-Head (Alibaba group) | [Website](https://occ.t-head.cn/vendor/cpu/index?id=3817197695983423488) | RV64 | 1.10 | RV64IMA[FD]C[V] + SV39 + ISA Extension + Memory model Extension | Verilog | Alibaba commercial license\nXuanTie E906 | T-Head (Alibaba group) | [Website](https://occ.t-head.cn/vendor/cpu/index?id=3806463049662468096) | RV32 | 1.10 | RV32IMA[F][D]C + ISA Extension| Verilog | Alibaba commercial license\nXuanTie E902 | T-Head (Alibaba group) | [Website](https://www.t-head.cn/product/e902?spm=a2ouz.12987052.0.0.5c5c6245R2yhfA) | RV32 | 1.10 | RV32EMC/IMC/EC | Verilog | Alibaba commercial license\nBM-310 | CloudBEAR | [Website](https://cloudbear.ru/bm_310.html) | RV32 | 1.10 | RV32IMC | SystemVerilog | CloudBEAR Commercial License\nBI-350 | CloudBEAR | [Website](https://cloudbear.ru/bi_350.html) | RV32 | 1.10 | RV32IMAFC + multi-core | SystemVerilog | CloudBEAR Commercial License\nBI-651 | CloudBEAR | [Website](https://cloudbear.ru/bi_651.html) | RV64 | 1.10 | RV64GC + multi-core | SystemVerilog | CloudBEAR Commercial License\nBI-671 | CloudBEAR | [Website](https://cloudbear.ru/bi_671.html) | RV64 | 1.10 | RV64GC + multi-core | SystemVerilog | CloudBEAR Commercial License\nSSRV | risclite | [Website](https://risclite.github.io/),[GitHub](https://github.com/risclite/SuperScalar-RISCV-CPU) | RV32 | 1.10 | RV32IMC | Verilog | Apache 2.0\nTinyriscv | Blue Liang | [GitHub](https://github.com/liangkangnan/tinyriscv) | RV32 |  | 2.1, RV32I | Verilog | Apache 2.0\nRSD | rsd-devel | [GitHub](https://github.com/rsd-devel/rsd) | RV32 |  | RV32IM | SystemVerilog | Apache 2.0\nPluto | PQShield | [Website](https://pqsoc.com) | RV32 | 1.11 | RV32I[M][C] / RV32E[M][C] + Crypto Functions | Verilog | PQShield Commercial License\nE2 | SiFive | [Website](https://www.sifive.com/cores/e24) | RV32 | 1.11 | RV32I(E)MAFC 2.2 | Verilog | SiFive commercial license\nS2 | SiFive | [Website](https://www.sifive.com/cores/s21) | RV64 |1.11 | RV64GC 2.2 | Verilog | SiFive commercial license\nE3 | SiFive | [Website](https://www.sifive.com/cores/e34) | RV32 | 1.11 | RV32I(E)MAFDC 2.2 | Verilog | SiFive commercial license\nS5 | SiFive | [Website](https://www.sifive.com/cores/s54) | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license\nU5 | SiFive | [Website](https://www.sifive.com/cores/u54) | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license\nE7 | SiFive | [Website](https://www.sifive.com/cores/e76) | RV32 | 1.11 | RV32I(E)MAFDC 2.2 | Verilog | SiFive commercial license\nS7 | SiFive | [Website](https://www.sifive.com/cores/s76) | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license\nU7 | SiFive | [Website](https://www.sifive.com/cores/u74) | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license\nKronos | Sonal Pinto | [GitHub](https://github.com/SonalPinto/kronos) | RV32 | | RV32I | SystemVerilog | Apache 2.0\nN100 | Nuclei | [Website](https://www.nucleisys.com/product.php) | RV32 | 1.11 | RV32EC | Verilog | Nuclei commercial license\nN200 | Nuclei | [Website](https://www.nucleisys.com/product.php) | RV32 | 1.11 | RV32IC(E)(M)(A) | Verilog | Nuclei commercial license\nN300 | Nuclei | [Website](https://www.nucleisys.com/product.php) | RV32 | 1.11 | RV32IMAC(F)(D)(P) | Verilog | Nuclei commercial license\nN600 | Nuclei | [Website](https://www.nucleisys.com/product.php) | RV32 | 1.11 | RV32IMAC(F)(D)(P) | Verilog | Nuclei commercial license\nNX600 | Nuclei | [Website](https://www.nucleisys.com/product.php) | RV32 | 1.11 | RV64IMAC(F)(D)(P) | Verilog | Nuclei commercial license\nUX600 | Nuclei | [Website](https://www.nucleisys.com/product.php) | RV64 | 1.11 | RV64IMAC(F)(D)(P) + MMU-SV39 | Verilog | Nuclei commercial license\nWH32 | UC Techip | [Website](https://www.uctechip.com/#product) | RV32 | 1.10 | RV32GCX | Chisel | UC Techip Commercial License\nWARP-V | Steve Hoover, Redwood EDA | [GitHub](https://github.com/stevehoover/warp-v) | RV32 |  | RV32I[M][F] | TL-Verilog | BSD\nNEORV32 | Stephan Nolting | [GitHub](https://github.com/stnolting/neorv32) | RV32 | 1.12-draft | 2.2, RV32[I/E][M][A][C][Zfinx][Zicsr][Zifencei] | VHDL | BSD\nSteel | Rafael Calcada | [GitHub](https://github.com/rafaelcalcada/steel-core) | RV32 | 1.11 | RV32IZicsr | Verilog | MIT License\nKlessydra-T13 | Digital Systems Lab at Sapienza University of Rome | [GitHub](https://github.com/klessydra/T13x) | RV32 | 1.11 | RV32[I/E][M][A] + Kless-Vect | VHDL-2008 | Solderpad Hardware License v. 0.51\nKlessydra-T03 | Digital Systems Lab at Sapienza University of Rome | [GitHub](https://github.com/klessydra/T03x) | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51\nKlessydra-T02 | Digital Systems Lab at Sapienza University of Rome | [GitHub](https://github.com/klessydra/T02x) | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51\nKlessydra-F03 | Digital Systems Lab at Sapienza University of Rome | [GitHub](https://github.com/klessydra/F03x) | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51\nMYTH Cores | MYTH Workshop students | [GitHub](https://github.com/stevehoover/RISC-V_MYTH_Workshop/blob/master/student_projects.md) | RV32 |  | RV32I | TL-Verilog | BSD\nStarsea_riscv | Starsea | [GitHub](https://github.com/haogwb/starsea_riscv) | RV32 | | RV32I | Verilog | Apache 2.0\nVEGA | C-DAC | [Website](https://vegaprocessors.in/) | RV32, RV64 | 1.10 |  2.2, RV[32/64]IMA[F][D][C], Multi-core | Bluespec | commercial\nNutShell | UCAS \u0026 ICT,CAS | [GitHub](https://github.com/OSCPU/NutShell) | RV64 | 1.11 | RV64IMAC | Chisel | Mulan Permissive Software License V2\nNOEL-V | Cobham Gaisler | [Website](https://www.gaisler.com/NOEL-V) | RV32,RV64 | 1.11 | RV32GC,RV64GC | VHDL | GPL, Commercial\n\n\n## SoC platforms\n\nName | Supplier | Links | Capability | Core | License\n---- | -------- | ----- | ---------- | ---- | -------\nRocket Chip | SiFive, UCB BAR | [GitHub](https://github.com/freechipsproject/rocket-chip),[Simulator](https://fires.im) | RV32 |Rocket | BSD\nLowRISC | lowRISC | [GitHub](https://github.com/lowRISC/lowrisc-chip) | RV32 | RV32IM | BSD\nPULPino | ETH Zurich, Università di Bologna | [Website](http://www.pulp-platform.org),[GitHub](https://github.com/pulp-platform/pulpino) | RV32 | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51\nPULPissimo | ETH Zurich, Università di Bologna | [Website](http://www.pulp-platform.org),[GitHub](https://github.com/pulp-platform/pulpissimo) | RV32 |RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51\nAriane SoC | ETH Zurich, Università di Bologna | [Website](http://www.pulp-platform.org),[GitHub](https://github.com/pulp-platform/ariane) | RV64 | Ariane | Solderpad Hardware License v. 0.51\nOPENPULP | ETH Zurich, Università di Bologna | [Website](http://www.pulp-platform.org),[GitHub](https://github.com/pulp-platform/pulp) | RV32 | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51\nHERO | ETH Zurich, Università di Bologna | [Website](http://www.pulp-platform.org),[GitHub](https://github.com/pulp-platform/bigpulp) | RV32 | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51\nOpenPiton + Ariane | Princeton Parallel Group, ETH Zurich, Università di Bologna | [Website](https://parallel.princeton.edu/openpiton/),[GitHub](https://github.com/PrincetonUniversity/openpiton) | RV64 | Ariane | Solderpad Hardware License v. 0.51, BSD\nBriey | SpinalHDL | [GitHub](https://github.com/SpinalHDL/VexRiscv#briey-soc) | RV32 | VexRiscv | MIT\nRiscy | AleksandarKostovic | [GitHub](https://github.com/AleksandarKostovic/Riscy-SoC) | RV64 | RV64I | MIT\nRaven | RTimothyEdwards, mkkassem (efabless.com) | [GitHub](https://github.com/efabless/picorv32-soc-raven) | RV32 | PicoRV32 | ISC\nPicoSoC | Clifford Wolf | [GitHub](https://github.com/cliffordwolf/picorv32/tree/master/picosoc) | RV32 | PicoRV32 | ISC\nIcicle | Graham Edgecombe | [GitHub](https://github.com/grahamedgecombe/icicle) | RV32 | RV32I | ISC\nMIV RV32IMA L1 AHB | Microchip | [Documentation](http://www.microsemi.com/index.php?option=com_docman\u0026task=doc_download\u0026gid=1243779), [IDE](https://www.microsemi.com/product-directory/design-tools/4879-softconsole), [Development Environment](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc) | RV32 | Rocket RV32IMA | Apache 2.0\nMIV RV32IMA L1 AXI | Microchip | [Documentation](http://www.microsemi.com/index.php?option=com_docman\u0026task=doc_download\u0026gid=1243780), [IDE](https://www.microsemi.com/product-directory/design-tools/4879-softconsole), [Development Environment](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc) | RV32 | Rocket RV32IMA | Apache 2.0\nMIV RV32IMAF L1 AHB | Microchip | [Documentation](http://www.microsemi.com/index.php?option=com_docman\u0026task=doc_download\u0026gid=1243781), [IDE](https://www.microsemi.com/product-directory/design-tools/4879-softconsole), [Development Environment](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc) | RV32 | Rocket RV32IMAF | Apache 2.0\nMIV RV32IMC | Microchip | [Documentation](https://www.microsemi.com/document-portal/doc_download/1244850-mi-vrv32imc), [IDE](https://www.microsemi.com/product-directory/design-tools/4879-softconsole), [Development Environment](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc) | RV32 | Submicron RV32I, RV32IC, RV32IM, RV32IMC | Apache 2.0\nFreeStart AE250 | Andes | [Website](http://freestart.andestech.com/) | RV32 | N22 | Andes FreeStart: Free for Evaluation\nStandard AE250 | Andes | [Website](http://www.andestech.com/en/products-solutions/andeshape-platforms/ae250-ahb-based-platform-pre-integrated-with-n22/), [IDE](http://www.andestech.com/en/products-solutions/andesight-ide/) | RV32 | N22 | Andes Commerical License\nAE350 | Andes | [Website](http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/), [IDE](http://www.andestech.com/en/products-solutions/andesight-ide/) | RV32,RV64 | N25F, D25F, A25, A25MP, NX25, AX25, AX25MP, A27, A27L2, AX27, AX27L2, N45, D45, A45, NX45, AX45 | Andes Commerical License\nSCR1 SDK | Syntacore | [GitHub](https://github.com/syntacore/scr1-sdk) | RV32 | SCR1, SCRx | SHL 2.0\nESP | SLD Group, Columbia University | [Website](https://esp.cs.columbia.edu), [GitHub](https://github.com/sld-columbia/esp) | RV64 | Ariane | Apache 2.0\nChipyard | UCB BAR | [GitHub](https://github.com/ucb-bar/chipyard),[Documentation](https://chipyard.readthedocs.io/en/latest/) | RV64 | Rocket, BOOM | BSD\nPQSoC | PQShield | [Website](https://pqsoc.com) | RV32 | Pluto | PQShield Commercial License\nKRZ | Sonal Pinto | [GitHub](https://github.com/SonalPinto/kronos) | RV32 | Kronos | Apache 2.0\nIOb-SoC | IObundle | [GitHub](https://github.com/IObundle/iob-soc) | RV32 | PicoRV32 | MIT\nSweRVolf | CHIPS Alliance | [GitHub](https://github.com/chipsalliance/Cores-SweRVolf) | RV32 | SweRV EH1, SweRV EL2 | Apache 2.0\nServant | Olof Kindgren | [GitHub](https://github.com/olofk/serv) | RV32 | SERV | ISC\nNEORV32 Processor | Stephan Nolting | [GitHub](https://github.com/stnolting/neorv32) | RV32 | NEORV32 | BSD\nGRLIB | Cobham Gaisler | [Website](https://www.gaisler.com/getgrlib) | RV32,RV64 | NOEL-V | GPL, Commercial\nLiteX | Enjoy Digital | [Website](http://www.enjoy-digital.fr/), [GitHub](https://github.com/enjoy-digital/litex/) | RV32,RV64 | BlackParrot, CV32E40P, Minerva, PicoRV32, Rocket, SERV, VexRiscv (SMP supported with VexRiscv) | BSD\n\n## SoCs\n\nInclude a chip if it has been fabricated and is either available for sale, available for preorder, or running production workloads internally, and if it has at least one RISC-V hard core (no FPGAs, but non-\"SoC\" products\n with controller cores are allowed).\n\nName | Supplier | Links | Core | ISA | OS | Devkit | Availability\n---- | -------- | ----- | ---- | --- | -- | ------ | ------------\nFE310-G000 | SiFive | [Datasheet](https://static.dev.sifive.com/FE310-G000.pdf) | E31 | RV32IMAC | RTOS | [HiFive1](https://www.sifive.com/boards/hifive1) | public since 2016Q4\nFE310-G002 | SiFive | [Product page](https://www.sifive.com/boards/hifive1)  | E31 | RV32IMAC | RTOS | [HiFive1 Rev B](https://www.sifive.com/boards/hifive1-rev-b) | announced 2019Q1, available for preorder\nFreedom U540 | SiFive | [Product page](https://www.sifive.com/products/hifive-unleashed/) | U54 (4 cores), E51 (1 management core) | RV64GC (application cores), RV64IMAC (management core) | Linux | [HiFive Unleashed development board](https://www.sifive.com/boards/hifive-unleashed) | public since 2018Q1\nGAP8 | GreenWaves Technologies | [Product page](https://greenwaves-technologies.com/en/gap8-product/) | PULP / 1 + 8 RI5CY | RV32IMC (+ Priviledged and custom ISA extensions) | RTOS | [GAPuino development board](https://greenwaves-technologies.com/product/gapuino/) | public since 2018Q1\nK210 | Kendryte | [Product page](https://kendryte.com/#products), [Datasheet](https://s3.cn-north-1.amazonaws.com.cn/dl.kendryte.com/documents/kendryte_datasheet_20181011163248_en.pdf), [GitHub](https://github.com/kendryte) | K210 | RV64GC | Linux | [KD233 development board](https://www.analoglamb.com/product/dual-core-risc-v-64bit-k210-ai-board-kendryte-kd233/), [Sipeed MAIX/M1 development boards](https://www.seeedstudio.com/Artificial-Intelligence/Machine-Learning-c-1220/Computer-Vision-c-1221.html?product_list_order=name) | public since 2018Q4\nRV32M1 | NXP | [Reference Manual and Datasheet](https://github.com/open-isa-org/open-isa.org/tree/master/Reference%20Manual%20and%20Data%20Sheet) | RI5CY + Zero RI5CY + Arm Cortex M4F + Arm Cortex M0+ | RV32IMC | RTOS | [VEGAboard](https://open-isa.org/) | available for preorder as of 2018Q4\nRavenRV32 | efabless | [Datasheet](https://ef.link/raven), [GitHub](https://github.com/efabless/raven-picorv32) | PicoRV32 | RV32IMAC | RTOS | RavenRV32 DevKit | Limited Quantity\nPolarFire SoC | Microchip | [Product Page](https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga), [IDE with Renode platform](https://www.microsemi.com/product-directory/design-tools/4879-softconsole) | U54 (4 cores), E51 (management core) | RV64GC(U54), RV64IMAC(E51) | Linux | [Microchip Icicle Kit](https://www.microsemi.com/existing-parts/parts/152514), [HiFive Unleashed Expansion Board](https://www.microsemi.com/hifive-unleashed-expansion-board) | Icicle Kit ES available Q3 2020, HiFive Unleased Expansion Board - Q2 2018\nGD32VF103 | GigaDevice | [Product listing](https://www.gigadevice.com/products/product-finder/?fwp_processor_type=risc-v\u0026fwp_microcontrollers_product_line=mainstream\u0026fwp_microcontrollers_product_series=gd32vf103),[Datasheets](https://github.com/riscv-mcu/GD32VF103_DataSheets) | [Bumblebee Core](http://dl.sipeed.com/LONGAN/Nano/DOC/Bumblebee%20core%20datasheet_en.pdf) | RV32IMAC | RTOS | GD32VF103V-EVAL, [Longan Nano](http://longan.sipeed.com/) etc.| Public since 2019Q4\nCH572, CH573 | WCH | [Product Page](http://www.wch.cn/products/CH573.html) | RISC-V3A | RV32IMAC | RTOS | | public since 2019Q1\nCH32F103 | WCH | [Product Page](http://www.wch.cn/products/CH32V103.html) [Datasheet](http://www.wch.cn/downloads/file/311.html) | RISC-V3A | RV32IMAC | RTOS | | public since 2020Q2\nMiG-V | Hensoldt Cyber GmbH | [Product Page](https://hensoldt-cyber.com/mig-v/) | CV6A | RV64IMAC | [TrentOS](https://hensoldt-cyber.com/trentos/) |  | Limited\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Friscvarchive%2Friscv-cores-list","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Friscvarchive%2Friscv-cores-list","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Friscvarchive%2Friscv-cores-list/lists"}