{"id":23359692,"url":"https://github.com/risto97/zturn_linux","last_synced_at":"2025-06-25T08:33:27.265Z","repository":{"id":135834240,"uuid":"162352223","full_name":"Risto97/zturn_linux","owner":"Risto97","description":"Building linux kernel and u-boot for MYIR Z-Turn 7020 Zynq Board","archived":false,"fork":false,"pushed_at":"2019-02-23T14:49:16.000Z","size":175,"stargazers_count":10,"open_issues_count":1,"forks_count":7,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-24T09:21:12.435Z","etag":null,"topics":["fpga","linux-kernel","u-boot","vivado","xilinx","zturn","zynq"],"latest_commit_sha":null,"homepage":null,"language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Risto97.png","metadata":{"files":{"readme":"README.rst","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-12-18T22:25:40.000Z","updated_at":"2024-11-16T03:17:50.000Z","dependencies_parsed_at":"2023-04-12T14:57:42.378Z","dependency_job_id":null,"html_url":"https://github.com/Risto97/zturn_linux","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Risto97%2Fzturn_linux","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Risto97%2Fzturn_linux/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Risto97%2Fzturn_linux/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Risto97%2Fzturn_linux/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Risto97","download_url":"https://codeload.github.com/Risto97/zturn_linux/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248199136,"owners_count":21063641,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","linux-kernel","u-boot","vivado","xilinx","zturn","zynq"],"created_at":"2024-12-21T11:11:40.780Z","updated_at":"2025-04-10T10:32:03.544Z","avatar_url":"https://github.com/Risto97.png","language":"Tcl","funding_links":[],"categories":[],"sub_categories":[],"readme":"=====================================================\nLinux on Z-Turn board with free HDMI video controller\n=====================================================\n\nMYIR released video core for HDMI without time limitation.\nThis guide will provide explanations on how to compile U-Boot, Linux Kernel and add your own peripheral to your Linux design.\n\n**Clone git repos**\n\n.. code-block:: bash\n\n   ./clone_gits.sh\n\n**Export hardware and launch SDK**\n\nIn Vivado: File \u003e Export \u003e Export Hardware \u003e Check Include Bitstream \u003e OK\nIn Vivado: File \u003e Launch SDK\n\n**Create FSBL**\n\nIn SDK: File \u003e New \u003e Application Project\nProject Name: fsbl\nOS Platform: standalone\nHW platform: (select exported platform name**\n\n\u003e Next\nSelect Zynq FSBL\n\u003e Finish\n\n**Import video configuration files into FSBL**\n\nin FSBL src, right click import \u003e General \u003e File System.\n\nSelect fsbl/src from git folder. And import fsbl_hooks.c display_init/ sii0922_init/\n\nCheck Overwrite existing resources without warning. \u003e Finish\n\n\n**Add devicetree_generator to Xilinx SDK**\n\nIn SDK:\nSDK Menu: Xilinx \u003e Repositories \u003e New... (\u003c devicetree_git path\u003e) \u003e OK\n\n**Generate devicetree using Xilinx SDK**\n\nIn SDK:\nSDK Menu: File \u003e New \u003e Board Support Package \u003e Under Board Support Package OS, select device_tree \u003e finish\n\n**Modify devicetree files for framebuffer**\n\nIn file system-top.dtsi\n\nin section chosen{} after stdout-path = \"serial0:115200n8\"; append\n\n.. code-block:: bash\n\n\n   #address-cells = \u003c0x1\u003e;\n   #size-cells = \u003c0x1\u003e;\n   ranges;\n   framebuffer0: framebuffer@3F000000 {\n                compatible = \"simple-framebuffer\";\n                reg = \u003c0x3F000000 (1920*1080*4)\u003e;\n                width = \u003c1920\u003e;\n                height = \u003c1080\u003e;\n                stride = \u003c(1920*4)\u003e;\n                format = \"a8r8g8b8\";\n                status = \"okay\";\n   };\n\nIn section memory{}, change from reg = \u003c0x0 0x40000000\u003e; to reg = \u003c0x0 0x3F000000\u003e;\n\n**Fix bug in devicetree generated files**\n\nIt seems that Xilinx devicetree generator has a bug, it happens where there are multiple clock-names in a cell.\n\nIn file pl.dtsi watch for clock-names\n\n.. code-block:: bash\n\n      incorrect\n\t\t\tclock-names = \"s_axi_lite_aclk\", \"m_axi_mm2s_aclk\", \"m_axis_mm2s_aclk\";\n\n      correct\n\t\t\tclock-names = \"s_axi_lite_aclk m_axi_mm2s_aclk m_axis_mm2s_aclk\";\n\n**Add usb-otg support in devicetree**\n\nIn zynq-7000.dtsi replace usb0 entry without\n\n.. code-block:: bash\n\n\t\tusb0: usb@e0002000 {\n\t\t\tcompatible = \"xlnx,zynq-usb-2.20a\", \"chipidea,usb2\";\n\t\t\tstatus = \"okay\";\n\t\t\tclocks = \u003c\u0026clkc 28\u003e;\n\t\t\tinterrupt-parent = \u003c\u0026intc\u003e;\n\t\t\tinterrupts = \u003c0 21 4\u003e;\n\t\t\treg = \u003c0xe0002000 0x1000\u003e;\n\t\t\tphy_type = \"ulpi\";\n\t\t\tusb-reset = \u003c0x7 0x7 0x0\u003e;\n\t\t\tdr_mode = \"host\";\n\t\t\tusb-phy = \u003c0x6\u003e;\n\t\t};\n\nIn system-top.dts add phy0 after memory{}\n\n.. code-block:: bash\n\n\tphy0 {\n\t\tcompatible = \"ulpi-phy\";\n\t\t#phy-cells = \u003c0x0\u003e;\n\t\treg = \u003c0xe0002000 0x1000\u003e;\n\t\tview-port = \u003c0x170\u003e;\n\t\tdrv-vbus;\n\t\tlinux,phandle = \u003c0x6\u003e;\n\t\tphandle = \u003c0x6\u003e;\n\t};\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fristo97%2Fzturn_linux","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fristo97%2Fzturn_linux","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fristo97%2Fzturn_linux/lists"}