{"id":23812550,"url":"https://github.com/rj45/digilogic","last_synced_at":"2026-03-16T17:31:41.405Z","repository":{"id":61118411,"uuid":"548397933","full_name":"rj45/digilogic","owner":"rj45","description":"digilogic is a high speed digital circuit simulator / schematic capture","archived":false,"fork":false,"pushed_at":"2024-05-22T02:44:23.000Z","size":3621,"stargazers_count":9,"open_issues_count":3,"forks_count":1,"subscribers_count":3,"default_branch":"main","last_synced_at":"2024-05-22T19:17:27.713Z","etag":null,"topics":["circuit","digital","eda","logic","logic-gates","schematic-capture","simulation"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rj45.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":".github/FUNDING.yml","license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null},"funding":{"github":"rj45","ko_fi":"rj45_creates","patreon":"rj45Creates"}},"created_at":"2022-10-09T13:43:08.000Z","updated_at":"2024-05-27T17:59:54.278Z","dependencies_parsed_at":"2024-05-27T17:59:49.536Z","dependency_job_id":"9bae1c07-56cf-4f08-98b1-59310d4bb475","html_url":"https://github.com/rj45/digilogic","commit_stats":{"total_commits":4,"total_committers":1,"mean_commits":4.0,"dds":0.0,"last_synced_commit":"1616f2b7f3ebd6fe0e878a628dddf529a9c9f59d"},"previous_names":[],"tags_count":22,"template":false,"template_full_name":null,"purl":"pkg:github/rj45/digilogic","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rj45%2Fdigilogic","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rj45%2Fdigilogic/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rj45%2Fdigilogic/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rj45%2Fdigilogic/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rj45","download_url":"https://codeload.github.com/rj45/digilogic/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rj45%2Fdigilogic/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":273965092,"owners_count":25199199,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-09-06T02:00:13.247Z","response_time":2576,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["circuit","digital","eda","logic","logic-gates","schematic-capture","simulation"],"created_at":"2025-01-02T02:30:31.028Z","updated_at":"2026-03-16T17:31:41.378Z","avatar_url":"https://github.com/rj45.png","language":"C","funding_links":["https://github.com/sponsors/rj45","https://ko-fi.com/rj45_creates","https://patreon.com/rj45Creates"],"categories":[],"sub_categories":[],"readme":"# digilogic\n\nA digital logic simulation and schematic capture program.\n\n- With the following features:\n    - Wire auto-routing\n    - Alignment based snapping (rather than grid based)\n    - First class dark mode support\n    - Cross platform (Windows, Mac, Linux)\n    - Import from verilog via Yosys with auto layout and routing\n    - Import from H. Neeman's [Digital](https://github.com/hneemann/Digital)\n    - Written in Rust\n- Inspirations:\n    - [Issie](https://github.com/tomcl/issie)\n    - [Digital Logic Sim](https://github.com/SebLague/Digital-Logic-Sim)\n    - [Digital](https://github.com/hneemann/Digital)\n    - [LogiSim Evolution](https://github.com/logisim-evolution/logisim-evolution)\n\n## Status\n\nThis is under heavy development.\n\nThe only editing feature implemented so far is moving components around.\n\nCurrently, importing a Digital circuit works as long as it:\n- Contains no rotated components\n- Only uses Inputs, Outputs, And, Or, Xor and Not\n- All wires/components are 1 bit wide\n- Contains no embedded circuits\n\nYosys import works with similar constraints:\n- Only produces And, Or, Xor and Not gates\n- Only a single module with input and output ports (but no inout ports)\n\n## Building / Running\n\nInstall rust via rustup, then:\n\n```sh\ncargo run\n```\n\nTo run the simulation server (required to simulate circuits) run this in a separate terminal:\n\n```sh\ncargo run -- server\n```\n\n## Yosys Import\n\nUse the following command to generate an *unoptimized* yosys file for import:\n\n```sh\nyosys -p \"read_verilog \u003cINPUT_VERILOG\u003e.v; hierarchy -auto-top; proc; opt_clean; fsm -expand; memory -nomap; wreduce -memx; opt_clean; write_json \u003cOUTPUT_FILE\u003e.yosys\"\n```\n\nTo have yosys do some basic optimizations on the verilog, use this command:\n\n```sh\nyosys -p \"read_verilog \u003cINPUT_VERILOG\u003e.v; hierarchy -auto-top; proc; opt; fsm -expand; memory -nomap; wreduce -memx; opt; write_json \u003cOUTPUT_FILE\u003e.yosys\"\n```\n\nIf it crashes/errors on loading, it likely contains components that have not been implemented yet. Simplify your verilog until it works.\n\n## Code Overview\n\nThe architecture is kind of an onion-like layered architecture with core at the center, and the main crate on the outermost layer. But there's a few lumps where simulation, automatic routing and layout, and other features live. More information can be found in the [docs folder](./docs/).\n\nThis app is built like a game, using game engine technology. We're using [Bevy ECS](https://docs.rs/bevy_ecs/latest/bevy_ecs/) to allow the code to be more modular. We also use [Bevy App Plugins](https://bevy-cheatbook.github.io/programming/plugins.html). I highly recommend reading through the `Unofficial Bevy Cheatbook`'s chapter on the [Bevy Programming Framework](https://bevy-cheatbook.github.io/programming.html) which covers the fundamental building blocks we're using.\n\nMost crates in the [crates](./crates/) folder are also bevy plugins. Anything that's used by several crates should be moved into [core](./crates/digilogic_core/) rather than building a spider web of dependencies between crates that will be difficult to untangle later.\n\nFor windowing and UI we use [eframe](https://docs.rs/eframe/latest/eframe/) and [egui](https://docs.rs/egui/latest/egui/). For all graphics in the main schematic viewport, we use [vello](https://docs.rs/vello/latest/vello/) in order to render as much on the GPU as we can (this is why it's fast, even in debug mode).\n\n```plaintext\n.\n├── assets -- Images, fonts and other resources\n└── crates -- Main crates, set up as a mono-repo of sorts\n    ├── digilogic -- Main crate with UI, drawing and window management\n    │   ├── assets\n    │   │   ├── schemalib -- SVG symbols from the wonderful schemalib project\n    │   │   │   └── symbols\n    │   │   └── testdata -- Some example project files for testing\n    │   └── src -- Source code for the main crate\n    │       └── ui -- UI related code\n    ├── digilogic_core -- The core data types, used by most crates\n    │   └── src\n    ├── digilogic_gsim -- The simulation engine\n    │   └── src\n    ├── digilogic_layout -- Automatic layout code, mainly used when importing verilog\n    │   └── src\n    ├── digilogic_netcode -- The netcode connecting the simulation server and UI\n    │   └── src\n    ├── digilogic_routing -- Automatic wire routing code\n    │   └── src\n    ├── digilogic_serde -- Import / Export code for Digital and Yosys (Verilog)\n    │   ├── src\n    │   │   ├── digital\n    │   │   ├── json\n    │   │   └── yosys\n    │   └── testdata\n    └── digilogic_ux -- The UX (User eXperience) code -- sits between ui and core\n        └── src\n```\n\nAgain, more information can be found in the [docs folder](./docs/) if you want to learn more.\n\n## Credits\n\nThe vast majority of the code in this repo is written by [Mathis Rech](https://github.com/Artentus), especially the simulation engine and auto-router.\n\nI (rj45) mainly wrote the import code, UX code, and did lots of project management / design type stuff.\n\n## License\n\nApache 2.0, see [LICENSE](./LICENSE).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frj45%2Fdigilogic","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frj45%2Fdigilogic","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frj45%2Fdigilogic/lists"}