{"id":25268929,"url":"https://github.com/rnayabed/sutra-1","last_synced_at":"2025-07-09T03:09:22.487Z","repository":{"id":273989929,"uuid":"844861033","full_name":"rnayabed/sutra-1","owner":"rnayabed","description":"10-bit CPU \u0026 Assembler","archived":false,"fork":false,"pushed_at":"2025-01-25T13:08:58.000Z","size":2859,"stargazers_count":73,"open_issues_count":0,"forks_count":5,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-07-03T06:12:29.666Z","etag":null,"topics":["cpu","digital","digital-systems","hardware","logisim-cpu","logisim-evolution"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rnayabed.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-08-20T05:38:18.000Z","updated_at":"2025-06-30T10:18:26.000Z","dependencies_parsed_at":"2025-02-12T10:42:20.054Z","dependency_job_id":"c3d1fc4c-8d12-4b8f-9191-0bc71baa8561","html_url":"https://github.com/rnayabed/sutra-1","commit_stats":null,"previous_names":["rnayabed/sutra-1"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/rnayabed/sutra-1","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rnayabed%2Fsutra-1","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rnayabed%2Fsutra-1/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rnayabed%2Fsutra-1/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rnayabed%2Fsutra-1/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rnayabed","download_url":"https://codeload.github.com/rnayabed/sutra-1/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rnayabed%2Fsutra-1/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":264384311,"owners_count":23599610,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","digital","digital-systems","hardware","logisim-cpu","logisim-evolution"],"created_at":"2025-02-12T10:39:16.629Z","updated_at":"2025-07-09T03:09:22.447Z","avatar_url":"https://github.com/rnayabed.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003cdiv align=\"center\"\u003e\n\n# Sutra-1 / সুত্র-1 / सूत्र-1\n\n*10-bit CPU and Assembler*\n\n\u003cimg src=\"https://raw.githubusercontent.com/rnayabed/sutra-1/refs/heads/master/screenshots/main.png\" alt=\"Sutra-1 Main Screenshot\"\u003e\n\n### [Demonstration Video](https://youtu.be/2qCsluuu69Y)\n\n\u003c/div\u003e\n\n## Introduction\n\nI wanted to apply the concepts I had learnt in my Digital Systems classes and put together a basic turing machine. Projects such as [Nand2Tetris](https://www.nand2tetris.org/) and [Ben Eater's 8-bit Breadboard computer](https://www.youtube.com/@BenEater) also motivated me to make my own. \n\nDue to no prior knowledge of a Hardware Description Language and being a beginner in the world of Digital Systems, I used [Logisim Evolution](https://github.com/logisim-evolution/logisim-evolution) to build the system. \n\nI insisted on building every discrete component from scratch (instead of using built-in components) and with NAND gates only, to keep myself true to the Nand2Tetris course. Only the display was built from built-in components as it is considered an I/O device and not a part of the CPU.\n\n## Components\n\nThis project is consists of two parts\n- Hardware: The main digital logic design, made in Logisim Evolution, saved as `sutra_1.circ` \n- Software\n    - রচয়িতা / Rochoyita `rochoyita.py`: Assembler. [Rochoyita Documentation](https://github.com/rnayabed/sutra-1/blob/master/docs/rochoyita.md)\n    - শিল্পী / Shilpi `shipli.py`: Image generator for the 64x32 1-bit demo display. [Shilpi Documentation](https://github.com/rnayabed/sutra-1/blob/master/docs/display.md#Shilpi)\n\n## Specifications\n\n- Single core, in-order, non pipelined\n- RISC design: All instructions are 10-bits and executed within one cycle\n- 10-bit data bus\n- 20-bit address bus\n- 1 General Purpose Shift Register and Accumulator(A)\n- 3 General Purpose Registers (B, C, D)\n- Flag Based ALU with hardware NAND/ADD/SUBTRACT\n- IO\n    - 64x32 1-bit display\n    - 4 interrupt lines\n    - 10-bit output bus\n- Stack support\n- Hardware and Software Interrupts with Masking support\n\n## Documentation\n\n- [Example programs](https://github.com/rnayabed/sutra-1/blob/master/examples/README.md)\n- [Instruction Set Architecture](https://github.com/rnayabed/sutra-1/blob/master/docs/ISA.md)\n- [Rochoyita Assembler](https://github.com/rnayabed/sutra-1/blob/master/docs/rochoyita.md)\n- [Interrupts](https://github.com/rnayabed/sutra-1/blob/master/docs/interrupts.md)\n- [Display](https://github.com/rnayabed/sutra-1/blob/master/docs/display.md)\n- [Stack](https://github.com/rnayabed/sutra-1/blob/master/docs/stack.md)\n- [Memory](https://github.com/rnayabed/sutra-1/blob/master/docs/stack.md)\n\n## Future plans\n\n- Implement this on an FPGA\n- Add pipelining\n- Add out of order execution\n- Make it superscalar\n\n## Special thanks\n\n- [Nand2Tetris](https://www.nand2tetris.org/)\n- [EE102](https://study.iitm.ac.in/es/course_pages/EE1102.html)\n- [Lorenzo's Logisim-Evolution Fork](https://github.com/lorenzonotaro/logisim-evolution/tree/main) for faster simulation clock speed\n\n## License\n\nAll components and designs are licensed under the [GNU General Public License v3.0](https://github.com/rnayabed/sutra-1/blob/master/LICENSE).","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frnayabed%2Fsutra-1","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frnayabed%2Fsutra-1","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frnayabed%2Fsutra-1/lists"}