{"id":30554686,"url":"https://github.com/robert-riordan-ucd/8_bit_cpu_fpga","last_synced_at":"2025-08-28T04:20:51.478Z","repository":{"id":310475115,"uuid":"1012177079","full_name":"Robert-Riordan-UCD/8_Bit_CPU_FPGA","owner":"Robert-Riordan-UCD","description":null,"archived":false,"fork":false,"pushed_at":"2025-08-18T10:39:16.000Z","size":27379,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2025-08-18T11:41:11.085Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Robert-Riordan-UCD.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2025-07-02T00:08:18.000Z","updated_at":"2025-08-18T10:39:21.000Z","dependencies_parsed_at":"2025-08-18T11:51:13.374Z","dependency_job_id":null,"html_url":"https://github.com/Robert-Riordan-UCD/8_Bit_CPU_FPGA","commit_stats":null,"previous_names":["robert-riordan-ucd/8_bit_cpu_fpga"],"tags_count":null,"template":false,"template_full_name":null,"purl":"pkg:github/Robert-Riordan-UCD/8_Bit_CPU_FPGA","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Robert-Riordan-UCD%2F8_Bit_CPU_FPGA","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Robert-Riordan-UCD%2F8_Bit_CPU_FPGA/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Robert-Riordan-UCD%2F8_Bit_CPU_FPGA/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Robert-Riordan-UCD%2F8_Bit_CPU_FPGA/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Robert-Riordan-UCD","download_url":"https://codeload.github.com/Robert-Riordan-UCD/8_Bit_CPU_FPGA/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Robert-Riordan-UCD%2F8_Bit_CPU_FPGA/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":272436552,"owners_count":24934777,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-28T02:00:10.768Z","response_time":74,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-08-28T04:20:19.662Z","updated_at":"2025-08-28T04:20:51.462Z","avatar_url":"https://github.com/Robert-Riordan-UCD.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# 8 Bit FPGA CPU\n\nThis is an 8-bit CPU design running on a Tang Nano 9k FPGA. The CPU design is based on [Ben Eaters Breadboard CPU](https://eater.net/8bit), which is based on the [Simple As Possible Computer](https://en.wikipedia.org/wiki/Simple-As-Possible_computer).\n\nThe CPU is made of 11 modules, which are designed in SystemVerilog and verified using [pyuvm](https://github.com/pyuvm/pyuvm).\n\nThis is a gif of the CPU calculating the fibonacci sequence and displaying it (in hexadecimal).\n![Video of the CPU calculating the fibonacci sequence](fib.gif)\n\n# Getting Started\n\nThis project is not fully complete yet and is currently only tested on my personal laptop and raspberry pi. However, this is the current process. (I am developing on Ubuntu 24 and used [this](https://www.geeklan.co.uk/?p=2919) guide to get up and running using an open source toolchain)\n\n## Installation and Setup\n\nThe following programs are required:\n1. ```yosys``` for synthisis.\n2. ```nextpnr``` for place and route, and bitstream generation.\n3. ```openFPGALoader``` for loading the bitstream.\n\n```sudo apt insatll yosys nextpnr-gowin openfpgaloader```\n\nClone and navigate to the repository\n\n```\ngit clone https://github.com/Robert-Riordan-UCD/8_Bit_CPU_FPGA\ncd ./8_Bit_CPU_FPGA/\n```\n\n## Running\n\n```make all upload```\n\n## Testing\n\n```pyuvm``` is required for testing.\n\n```sudo apt install pyuvm```\n\nTo test each module navigate to the verif directory for that module and run make.\n\n```\ncd ./verif/\u003cmodule\u003e/\nmake\n```\n\n# Current Design Status\n\n| Module                  | RTL | Verified | Runs on FPGA |\n| :---------------------- | :-: | :-: | :-: |\n| Clock                   |✅|✅|✅|\n| Program Counter         |✅|✅|✅|\n| A register              |✅|✅|✅|\n| B Register              |✅|✅|✅|\n| Memory Address Register |✅|✅|✅|\n| Instruction Register    |✅|✅|✅|\n| Random Access Memory    |✅|✅|✅|\n| Arithmetic Logic Unit   |✅|✅|✅|\n| Control                 |✅|✅|✅|\n| Output                  |✅|✅|✅|\n| Bus                     |✅|✅|✅|\n| Bootloader              |✅|❌|❌|\n||||\n| Top                     |✅|❌|✅|\n\nThe output is currently in hexadecimal, because there was not enough LUTs on the Tang Nano 9k to implement a naive approach to decimal conversion using division. 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