{"id":15007310,"url":"https://github.com/robseb/meta-intelfpga","last_synced_at":"2025-10-30T11:31:44.081Z","repository":{"id":49813129,"uuid":"271601586","full_name":"robseb/meta-intelfpga","owner":"robseb","description":"Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide ","archived":false,"fork":false,"pushed_at":"2024-05-23T21:36:26.000Z","size":614,"stargazers_count":21,"open_issues_count":0,"forks_count":8,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-02-02T08:11:48.757Z","etag":null,"topics":["altera","arria-v","arria10","bsp-layer","cyclone-v","development-tools","fpga-configuration","fpga-fabric","intel-fpga","intel-soc-fpgas","linux-distribution","rsyocto","soc-fpga","soc-fpga-linux","yocto-layer","yocto-meta"],"latest_commit_sha":null,"homepage":"https://layers.openembedded.org/layerindex/branch/master/layer/meta-intelfpga/","language":"BitBake","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/robseb.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"COPYING.MIT","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-06-11T17:00:46.000Z","updated_at":"2024-11-05T16:21:36.000Z","dependencies_parsed_at":"2024-05-19T14:48:50.074Z","dependency_job_id":null,"html_url":"https://github.com/robseb/meta-intelfpga","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/robseb%2Fmeta-intelfpga","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/robseb%2Fmeta-intelfpga/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/robseb%2Fmeta-intelfpga/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/robseb%2Fmeta-intelfpga/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/robseb","download_url":"https://codeload.github.com/robseb/meta-intelfpga/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":238960435,"owners_count":19559264,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera","arria-v","arria10","bsp-layer","cyclone-v","development-tools","fpga-configuration","fpga-fabric","intel-fpga","intel-soc-fpgas","linux-distribution","rsyocto","soc-fpga","soc-fpga-linux","yocto-layer","yocto-meta"],"created_at":"2024-09-24T19:08:09.606Z","updated_at":"2025-10-30T11:31:44.073Z","avatar_url":"https://github.com/robseb.png","language":"BitBake","funding_links":[],"categories":[],"sub_categories":[],"readme":"![GitHub](https://img.shields.io/static/v1?label=Plattform\u0026message=Altera+SoC-FPGA\u0026color=blue)\n![GitHub](https://img.shields.io/github/license/robseb/meta-intelfpga)\n\u003cbr\u003e\n\n# BSP meta-layer for Intel (*ALTERA*) SoC-FPGAs (*SoCFPGAs*) and the *Yocto Project* \n\n**With this layer the board support package (BSP) for *ARM* based *Altera (Intel) SoC-FPGAs (SoCFPGA)* is added to the *Yocto Project*.** \u003cbr\u003e\n**It can bring with the *rstools* useful tools to interact with the FPGA fabric (e.g. Changing the FPGA configuration or accessing all ARM AXI Bride interfaces).** \u003cbr\u003e\n**In addition, is the ARM Development Studio (*DS-5*) *Streamline* Server [*gator*](https://github.com/ARM-software/gator) included.**\n\nUsually the *Yocto Project* can generate all required components (*rootfs*, *device tree*, bootloaders,...) to boot up a final embedded Linux. But this is not compatible with [Intel's Boot flow](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an709.pdf).\nThis Bootflow uses the Intel *Embedded Design Suite* (*EDS*) to build the device tree and all necessary bootloaders. \n\nFor that reason, I designed a version that is compatible with *Intel's* development tools.  \nThis includes the board specific *u-boot-* and device tree-generation and the support for only the *.tar.gz*-file type for the *rootfs*. \n\nI used this layer to build [*rsyocto*](https://github.com/robseb/rsyocto), an open source embedded Linux Distribution for Intel SoC-FPGAs, by myself. \nThe flexibility of my own [**rsyocto build system**](https://github.com/robseb/rsyocto#build-system-for-generation-of-custom-rsyocto-flavors) allows you to use it for your own projects with your custom embedded Linux. \n \nFor instance with a single Linux shell command (`FPGA-writeConfig`) of the *rstools* it is possible to change FPGA configuration of a Intel *Cyclone V SoC-FPGA*: \u003cbr\u003e\n![Alt text](doc/FPGAConfigurationAction.gif?raw=true \"Write FPGA Configuration\")\n\n**More *rstools* examples are available [here inside my *rsyocto* guide](https://github.com/robseb/rsyocto/blob/rsyocto-1.042/doc/guides/2_FPGA_HARDIP.md#interacting-with-fpga-ip).**\n\n\n## Supported Device families\n\n| **Device Family** | **Architecture** | **Machine Name** |\n|:--|:--|:--|\n| Intel (*ALTERA*) **Cylone V** SoC-FPGA | *ARMv7A* | *MACHINE =\"cyclone5\"* |\n| Intel (*ALTERA*) **Arria 10** SoC-FPGA | *ARMv7A* | *MACHINE =\"arria10\"* |\n| Intel (*ALTERA*) **Stratix 10** SoC-FPGA | *ARMv8A* | *MACHINE =\"stratix10\"* |\n| Intel (*ALTERA*) **Agilex 3** SoC-FPGA | *ARMv8A* | *MACHINE =\"agilex3\"* |\n| Intel (*ALTERA*) **Agilex 5** SoC-FPGA | *ARMv8A* | *MACHINE =\"agilex5\"* |\n| Intel (*ALTERA*) **Agilex 7** SoC-FPGA | *ARMv8A* | *MACHINE =\"agilex7\"* |\n\u003cbr\u003e\n\n## Supported Yocto Project Releases \n\nAutomated CI/CD test system ensures compatibility with following *Yocto Project* releases:\n\n| **Release Version** | **Release Name** | **Integration Tested**|\n|:--|:--|:--|\n| `5.2` | `walnascar` | 05 SEP 2025 |\n| `5.1` | `styhead` | 05 SEP 2025 |\n| `5.0` | `scarthgap` | 05 SEP 2025 |\n| `4.3` | `nanbield` | 05 SEP 2025 |\n| `4.2` | `mickledore` | 05 SEP 2025 |\n| `4.1` | `langdale` | 05 SEP 2025 |\n| `4.0` | `kirkstone` | 05 SEP 2025 |\n\n\n\n## Linux Kernel Types\n\n| **Kernel Name** | **Upstream Kernel Version**  | **Implementation** | **Is LTS**  | **Integration Tested**|\n|:--|:--|:--|:--|:--|\n| linux-altera-lts | `6.12` | PREFERRED_VERSION_linux-altera-lts = \"6.12%\" | Yes | 05 SEP 2025 |\n| linux-altera | `6.7` | PREFERRED_VERSION_linux-altera = \"6.7%\" | No | 05 SEP 2025 |\n| linux-altera, linux-altera-lts | `6.6` | PREFERRED_VERSION_linux-altera-lts = \"6.6%\" | Yes | 05 SEP 2025 |\n| linux-altera | `6.5` | PREFERRED_VERSION_linux-altera = \"6.5%\" | No | 05 SEP 2025 |\n| linux-altera | `6.2` | PREFERRED_VERSION_linux-altera = \"6.2%\" | No | 05 SEP 2025 |\n| linux-altera, linux-altera-lts | `6.1` | PREFERRED_VERSION_linux-altera-lts = \"6.1%\" | Yes | 05 SEP 2025 |\n| linux-altera | `6.0` | PREFERRED_VERSION_linux-altera = \"6.0%\" | No | 05 SEP 2025 |\n| linux-altera | `5.19` | PREFERRED_VERSION_linux-altera = \"5.19%\" | No | 05 SEP 2025 |\n| linux-altera | `5.18` | PREFERRED_VERSION_linux-altera = \"5.18%\" | No | 05 SEP 2025 |\n| linux-altera | `5.17` | PREFERRED_VERSION_linux-altera = \"5.17%\" | No | 05 SEP 2025 |\n| linux-altera | `5.16` | PREFERRED_VERSION_linux-altera = \"5.16%\" | No | 05 SEP 2025 |\n| linux-altera, linux-altera-lts | `5.15` | PREFERRED_VERSION_linux-altera-lts = \"5.15%\" | Yes | 05 SEP 2025 |\n| linux-altera | `5.14` | PREFERRED_VERSION_linux-altera = \"5.14%\" | No | 05 SEP 2025 |\n| linux-altera | `5.13` | PREFERRED_VERSION_linux-altera = \"5.13%\" | No | 05 SEP 2025 |\n| linux-altera | `5.12` | PREFERRED_VERSION_linux-altera = \"5.12%\" | No | 05 SEP 2025 |\n| linux-altera | `5.11` | PREFERRED_VERSION_linux-altera = \"5.11%\" | No | 05 SEP 2025 |\n| linux-altera-lts | `5.10` | PREFERRED_VERSION_linux-altera-lts = \"5.10%\" | Yes | 05 SEP 2025 |\n| linux-altera | `5.9` | PREFERRED_VERSION_linux-altera = \"5.9%\" | No | 05 SEP 2025 |\n| linux-altera | `5.8` | PREFERRED_VERSION_linux-altera = \"5.8%\" | No | 05 SEP 2025 |\n| linux-altera | `5.7` | PREFERRED_VERSION_linux-altera = \"5.7%\" | No | 05 SEP 2025 |\n| linux-altera | `5.6` | PREFERRED_VERSION_linux-altera = \"5.6%\" | No | 05 SEP 2025 |\n| linux-altera | `5.5` | PREFERRED_VERSION_linux-altera = \"5.5%\" | No | 05 SEP 2025 |\n| linux-altera-lts | `5.4` | PREFERRED_VERSION_linux-altera-lts = \"5.4%\" | Yes | 05 SEP 2025 |\n\n\n## List of *rstools* to interact with the FPGA-fabric\n\n| **Linux Command Name** | **Description** | **CV** | **A10**  | **Bitbake value**\n|:--|:--|:--|:--|:--|\n|`FPGA-status` | **Reading the Status of the FPGA fabric** | :heavy_check_mark: | :heavy_check_mark: | *statusfpga* \n|`FPGA-readMSEL` | **Reading the Configuration mode of the FPGA (selected with the MSEL-Bit Switch)** | :heavy_check_mark: | :heavy_check_mark: | *mselfpga*\n|`FPGA-dumpbridge` | **Reading a address span from an address of an AXI Bridge interface or SDRAM** | :heavy_check_mark: | :x: | *dumpbridge* \n|`FPGA-resetFabric` | **Resetting the FPGA fabric (remove the FPGA running configuration)** | :heavy_check_mark: |:x: | *resetfabricfpga*\n|`FPGA-writeConfig` | **Writing a new FPGA configuration with a configuration file** | :heavy_check_mark: |:x: | *writeconfigfpga*\n|`FPGA-readBridge` | **Reading from an address of an AXI Bridge interface (*Lightweight HPS2FPGA* or *HPS2FPGA*) or form the *MPU* Address space** | :heavy_check_mark: | :heavy_check_mark: | *readbridgesfpga*\n|`FPGA-writeBridge` | **Writing to an address of an AXI Bridge interface (*Lightweight HPS2FPGA* or *HPS2FPGA*) or form the *MPU* Address space** | :heavy_check_mark: | :heavy_check_mark:  | *writebridgefpga*\n|`FPGA-gpiRead` | **Reading the 32 Bit direct access general purpose input Register (GPI) (written by the FPGA)** | :heavy_check_mark: |:x: | *readfgpipga*\n|`FPGA-gpoWrite` | **Writing the 32 Bit direct access general purpose output Register (GPO)** | :heavy_check_mark: |:x:  | *writegpofpga*\n\n\nThe source code of the *rstools* is available here: [For the Intel Cyclone V SoC-FPGA](https://github.com/robseb/rstoolsCY5) and [For the Intel Arria 10 SoC-FPGA](https://github.com/robseb/rstoolsA10)\n\u003cbr\u003e\n\n## List of available additional components \n\n| **Component Name** | **Description** | **Bitbake value**\n|:--|:--|:--|\n| `gator` | [**ARM Development Studio (*DS-5*) Streamline server**](https://github.com/ARM-software/gator) | *gator* \n| `initscript`| **Enables to execute various init scripts during Linux booting at different booting levels** | *initscript*\n\u003cbr\u003e\n\n**A Linux Kernel Configuration with an appropriate configuration to enable all ARM Core-Sight Debugging features for ARM Streamline will be automatically loaded.**\n\n## Choose your preferred ARM Development Studio (*DS-5*) Streamline server version\n| **Gator Version** | **Compatible ARM Streamline Version** | **Expression**\n|:--|:--|:--|\n| `8.6.0` | `Streamline 8.6.0` | PREFERRED_VERSION:gator = \"8.6.0\"\n| `8.0.0` | `Streamline 8.0.0` | PREFERRED_VERSION:gator = \"8.0.0\"\n| `7.8.0` | `Streamline 7.8.0` | PREFERRED_VERSION:gator = \"7.8.0\"\n\n\n## Tested Development Machine Setup\n\n* **OS**\n\t* **Ubuntu 20.04 LTS**\n\t* **Ubuntu 24.04 LTS**\n\n* **Yocto Project Releases**\n\t* ****kirkstone**, **langdale**, **mickledore**, **nanbield**, **scarthgap**, **styhead**, **walnascar**** (*5.0*)\n\n**Note:** Select the dedicated branch for the Yocto Project Release you want to use in this repository.\n\n\u003cbr\u003e\n\n\u003cbr\u003e\n\n## Getting started with the *Yocto Project* and use of this BSP-layer\n\nThe following step by step guide shows how to use this layer to build a Yocto-based Linux System for an *Intel SoC-FPGA*:\n1. Step: **Install the latest Version of the *OpenEmbedded Yocto Project***\n\t* As a Building machine use regular *Ubuntu-Linux* or **CentOS Linux** running as a *Virtual Machine* (VM)\n\t* Required components for the *Yocto Project* with **Ubuntu Linux**:\n\t\t````bash\n\t\tsudo apt-get -y install gawk wget libgmp3-dev libmpc-dev \\\n        git diffstat unzip texinfo gcc-multilib build-essential \\\n        chrpath socat xterm libsdl2-image-2.0-0 u-boot-tools \\\n        python3 python3-pip python3-pexpect \\\n        python3-git python3-jinja2 libncurses-dev zstd lz4\n\t\t````\n\t* Set local settings\n\t\t````bash\n\t\tsudo locale-gen en_US.UTF-8\n\t\texport LANG=en_US.UTF-8\n\t\texport LC_ALL=en_US.UTF-8\n\t\t````\t\n\t* **Optional:** Ubuntu Linux for usage of the *Arm Development Studio (DS-5)*\n\t\t````bash\n\t\tsudo apt-get install libncurses5\n\t\tsudo apt-get install zlib1g:i386\n\t\t\n\t\twget http://archive.ubuntu.com/ubuntu/pool/main/i/icu/libicu60_60.2-3ubuntu3_amd64.deb\n\t\tsudo apt install ./libicu60_60.2-3ubuntu3_amd64.deb\n\t\t\n\t\twget http://de.archive.ubuntu.com/ubuntu/pool/universe/w/webkitgtk/libjavascriptcoregtk-1.0-0_2.4.11-3ubuntu3_amd64.deb\n\t\tsudo apt install ./libjavascriptcoregtk-1.0-0_2.4.11-3ubuntu3_amd64.deb\n\t\t\n\t\twget http://security.ubuntu.com/ubuntu/pool/universe/w/webkitgtk/libwebkitgtk-1.0-0_2.4.11-3ubuntu3_amd64.deb\n\t\tsudo apt install ./libwebkitgtk-1.0-0_2.4.11-3ubuntu3_amd64.deb\n\t\t\n\t\tsudo apt-get install -y libc6-armel-cross libc6-dev-armel-cross binutils-arm-linux-gnueabi libncurses5-dev build-essential bison flex libssl-dev bc\n\t\t\n\t\tsudo apt-get install -y gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf  gcc-arm-linux-gnueabi g++-arm-linux-gnueabi\n\t\t````\n\t* Check your git version (it should be 2.24+)\n\t\t````bash\n\t\tgit --version\n\t\t````\n\t* Check your gcc version (it should be \u003e13.2.0) \n\t\t````bash\n\t\tgcc --version\n\t\t````\n\n\t* Install the *Yocto Project* itself in Release *5.0 \"scarthgap\"*\n\t\t````bash\n\t\tcd \u0026\u0026 git clone -b scarthgap git://git.yoctoproject.org/poky.git\n\t\t````\n    * Install the *OpenEmbedded* SDK Standalone Version\n        ````cmd\n        cd ~/poky \u0026\u0026 wget https://downloads.yoctoproject.org/releases/yocto/yocto-5.0/buildtools/x86_64-buildtools-nativesdk-standalone-5.0.sh \u0026\u0026 sh x86_64-buildtools-nativesdk-standalone-5.0.sh\n        ````\n        * Run the SDK environment script as shown in the previous command, e.g.: \n            ````cmd\n            source /opt/poky/5.0/environment-setup-x86_64-pokysdk-linux\n            ````\n2. Step: **Download this BSP-layer**\n\t````bash\n\tcd poky/ \u0026\u0026 git clone https://github.com/robseb/meta-intelfpga.git\n\t````\n\n3. Step: **Run the *bitbake* initialization script**\n\t````bash \n\tsource oe-init-build-env\n\t````\n\t* Do not run this command or any other Yocto commands as root!\n\t* Do not use the command: “*sudo ./ oe-init-build-env*”. With this line Bitbake crashes later during the build process without any traceable error message  \n\t* The script should create the folder: \"`/build`\"\n\n4. Step: **Add this BSP-layer to your Yocto Project solution**\n\t* Open the **\"bblayers.conf\"**-file *(poky/build/conf)* with a text editor for example with *MS Visual Studio Code*:\n\t\t````bash \n\t\tcode conf/bblayers.conf\n\t\t````\n\t* Add the following line to this file to include the BSP-layer:\n\t\t````bitbake\n\t\t/home/vm/poky/meta-intelfpga \\\n\t\t````\n\t\t* **Note:** Replace the user name *\"vm\"* with your user name\n\t* Now should the *\"bblayers.conf\"*-file look like this:\n\t\t````bitbake\n\t\t# POKY_BBLAYERS_CONF_VERSION is increased each time build/conf/bblayers.conf\n\t\t# changes incompatibly\n\t\tPOKY_BBLAYERS_CONF_VERSION = \"2\"\n\n\t\tBBPATH = \"${TOPDIR}\"\n\t\tBBFILES ?= \"\"\n\t\tBBLAYERS ?= \" \\\n\t\t  /home/vm/poky/meta \\\n\t\t  /home/vm/poky/meta-poky \\\n\t\t  /home/vm/poky/meta-yocto-bsp\\\n\t\t  /home/vm/poky/meta-intelfpga \\\n\t\t\"\n\t\t````\n5. Step: **Configure the machine type and Linux Version**\n\t* Open the **\"local.conf\"**-file *(poky/build/conf)* with a text editor, for example with *MS Visual Studio Code*:\n\t\t````bash \n\t\tcode conf/local.conf\n\t\t````\n\t* **Select your Intel SoC-FPGA family** by adding the value **\"MACHINE\"** to this configuration file\n\t\t* For the different devices use string of the table above\n\t\t* For example, for an Intel Cyclone V SoC-FPGA add following to this file:\n\t\t\t````bitbake\n\t\t\tMACHINE =\"cyclone5\"\n\t\t\t````\n\t\t* Be sure that default *\"qwmux86-64\"* is **removed**\n\t\t\t````bitbake\n\t\t\t# MACHINE ??= \"qemux86-64\"\n\t\t\t````\n\t* **Select the Linux Kernel type**\n\t\t* If you want to use the regular **ALTERA socfpga-Linux Kernel** add the line above to the **\"local.conf\"**-file:\n\t\t\t````bitbake\n\t\t\tPREFERRED_PROVIDER_virtual/kernel = \"linux-altera\"\n\t\t\t````\n\t\t* If you want the **long term stable (LTSI) ALTERA socfpga-Linux Kernel** use this line:\n\t\t\t````bitbake\n\t\t\tPREFERRED_PROVIDER_virtual/kernel = \"linux-altera-lts\"\n\t\t\t````\n\t* **Select the Linux Kernel Version**\n\t \t* With following code line it is possible to select the preferred Linux Kernel Version (here with *Version `6.1`*)\n\t\t\t````bibtabe\n\t\t\tPREFERRED_VERSION_linux-altera = \"6.1%\"\n\t\t\t````\n\t\t* Alternatively, to select the *Long term stable Linux Version* (*LTS*) `6.1.68` \n\t\t\t````bibtabe\n\t\t\tPREFERRED_VERSION_linux-altera = \"6.1.68%\"\n\n\t\t\t````\n\t\t* All supported Linux Kernel versions are listed above\n\t\t* Add these two lines to the **\"local.conf\"**-file independent of your chosen machine \n \t* **Select the used CPU Version**\n\t\t* For an Dual Core Intel (ALTERA) **Cyclone V SoC-FPGA**, **Arria V SoC-FPGA** or **Arria 10 SoC-FPGA** add the following line to the **\"local.conf\"**-file:\n\t\t````bibtabe\n\t\tDEFAULTTUNE = \"cortexa9hf-neon\"\n\t\t````\n\t\t* This selects the ARMv7 Cortex-A9 dual core CPU with the NEON-Engine and a vector floating-point unit\n\t* **Save and close this file**\n\t\n6. Step: **Check if your settings are vialed and executable**\n\t* The following shell-command lists all for this build used layers (executed inside *poky/build/*):\n\t\t````bibtabe\n\t\tbitbake-layers show-layers\n\t\t````\n\t\t* If an error occured certainly something with the \"**local.conf**- or \"**bblayers.conf\"**-file went wrong\n\t* This command gives the used Linux Kernel Version\n\t\t````bibtabe\n\t\tbitbake --show-versions | grep linux  \n\t\t````\n7. Step: **Optional: Change the Linux Kernel configuration**\n\t* To configure the Linux properly for a specific device family it is necessary to change the Linux Kernel configuration\n\t* But for a first *Yocto Project* build is the Linux Kernel configured well enough\n\t* Read and change the BSP-layer with **\"defcongig\"**\n\t\t* One part is configured by a \"*defconfig*-file\"\n\t\t* With that it is possible to enable or disabled every component, like for example ETHERNET, CAN, EXT2, HPS-Bridges and PCI\n\t\t* The following bitbake shell-command stores the \"*defconfig*-file locally (executed inside *poky/build/*)\n\t\t````bash\n\t\tbitbake -c savedefconfig virtual/kernel \n\t\t````\n\t\t* This command prints the directory of the saved file at the end\n\t* Read and change the Linux Kernel with **menueconfig**\n\t\t* Use this command to start the \"*menueconfiguration*\"-tool:\n\t\t````bash\n\t\tbitbake -c menuconfig -f virtual/kernel\n\t\t````\n\t\t* A window like this should appear: \n\t\t![Alt text](doc/LinuxKerneMenueConfigl.jpg?raw=true \"Linux Kernel menu Config\")\n\n\t\t\u003cbr\u003e\n\n\t\t* Here it is possible to change any kernel settings, ARM-Platform specific settings or enable or disable some peripherel components\n        * The *menueconfig* configuration will be stored on the same directory as the *defconfig*\n\t* To execute any BSP-layer change use the following command:\n\t\t````bash\n\t\tbitbake -f -c compile virtual/kernel \u0026\u0026 bitbake -f -c deploy virtual/kernel\n\t\t````\n8. Step: **Pre-install additional tools, like my *rstools* to interact with the FPGA configuration**\n    * To pre-install addional components from this metal-layer it is only necessary to add the *Bitbake value* (*as shown in the tables above*) to the *local.conf* file\n    * For instance to pre-install the ARM *Streamline* `gator` Server insert the following line to *local.conf* (*poky/build/conf/local.conf*)\n    ```bash\n\tIMAGE_INSTALL:append = \" gator \"\n\t``` \n    * For installing all *rstools* use the following term\n    ```bash\n\tIMAGE_INSTALL:append = \" mselfpga readbridgesfpga resetfabricfpga statusfpga writebridgefpga writeconfigfpga writegpofpga readfgpipga \"\n\t``` \n9. Step: **Optional: Configure BusyBox**\n\t* `BusyBox` is a Linux Software that can bring the typical Linux Console envivonment as simple In-/Output interface to enable a basic user interaction\n\t* The *core-image-minimal* image installs automatically `BusyBox` with a basic set of classical commands, such as `ls`, `cd`\n\t* With the following term it will be enabled to add additional commands to `BusyBox` \n\t```bash\n\tbitbake -c menuconfig busybox\n\t```\n    * If you want to save the `busybox`, the configuration file is written to a location as follows: `~/poky/build/tmp/work/cortexa9hf-neon-poky-linux-gnueabi/busybox/1.31.1-r0/busybox-1.31.1/`\n10. Step: **Build the entire Yocto Project**\n\t* With this command the complete *Yocto Project* build process starts (executed inside *poky/build/*): \n\t````bash\n\tbitbake core-image-minimal\n\t````\n\t* This process can taken some time\n\t* For an *Intel Arria 10 SoC-FPGA* the following start print should appear:\n\t![Alt text](doc/YoctoBuildHeader.jpg?raw=true \"Yocto Project startup print\")\n\n\t* This signaled that bitbake was able to decode the previously shown configuration \n11. Step: **Locate the final Kernel- and rootfs-File** \n\t* After a successful build the final compressed Linux Kernel file and the *rootfs* \"*tar.gz*\"- archive is stored here: \n\t\t* for an **Intel Cyclone V SoC-FPGA:**\n\t\t````txt\n\t\tpoky/build/tmp/delopy/images/cyclone5/\n\t\t````\n\t\t* for an **Intel Arria 10 SX SoC-FPGA:**\n\t\t````txt\n\t\tpoky/build/tmp/delopy/images/arria10/\n\t\t````\n\t* The rootFs-file is called: **core-image-minimal-cyclone5-\u003c*Date Code*\u003e.rootfs.tar.gz**\n\t* The Linux Kernel file is called: **zImage-\u003c...+\u003e.bin**\n\t* Be sure that the files are **not a Shortcut**!\n\t* In the case of an *Intel Cyclone V* SoC-FPGA, these two files are located here:\n\t![Alt text](doc/YocotoOutput.jpg?raw=true \"Yocto Project output\")\n\n\u003cbr\u003e\n\nAt this point a Linux for an *Intel SoC-FPGA* is generated. Unfortunately to boot this up also a *Linux Device Tree*, a primary- and secondary bootloader and for *Intel Arria* and *Intel Stratix* SoC-FPGAs two FPGA configuration files must be required.\n\u003cbr\u003e\n\n# Continuation\n\n### How to desgin the requiered bootloaders and the *DeviceTree* with Intel EDS ?\nInside my \"*Mapping HPS Peripherels*, like *I²C* or *CAN*, over the *FPGA* fabric to *FPGA I/O* and using embedded Linux to control them\"-guide I show that in details \n(see [here](https://github.com/robseb/HPS2FPGAmapping)).\n\u003cbr\u003e\n\n\n### How to embedded Python pip packages to a Yocto Project?\n\nI also wrote a python script to **pre-install Python pip (PyPI)- Packages within a final Yocto Project Linux Image** automatically \n(see [here](https://github.com/robseb/PiP2Bitbake)).\n\u003cbr\u003e\n\n### How to bring the output files to a bootable image?\n\n![Alt text](doc/BuildSystemHead.png?raw=true \"Symbol of the build system\")\n**Build System: Use your *Intel Quartus Prime* FPGA project to create your own *rsyocto* with your FPGA Configuration**\n___\n\nI designed a Python script that can automate the boot image desgin with a specifiable partition table.\nIt can generate a bootable image file with Kernel-,bootloader- and user-files. With the flexibility of this script it is compatible with *Intel* SoC-EDS **build flow** for example it can pre-install FPGA configuration files.   \nTools like \"rufus\" can write for instance a SD-card to enable the booting of a Linux Distribution.\n(see [here LinuxBootImageGenerator](https://github.com/robseb/LinuxBootImageGenerator)).\n \nThe ***rsyocto* build system** can use the information provided by the *Intel Quartus Prime* FPGA project to compile and configure the bootloader (*u-boot*) to boot up an embedded Linux and to configure the FPGA Fabric with the *Intel Quartus Prime FPGA project*. The **build system** changes the rootfs of the embedded Linux und uses XML-files for configuration to automate every essential step to achieve a good experience of a modern Linux Distribution. \n**It can directly use output files of the Yocto Project to generate a custom bootable Linux Distribution for Intel Cylone V- and Intel Arria 10 SX SoC-FPGAs.**\nPlease follow my [**detailed guide**](https://github.com/robseb/rsyocto/blob/rsYocto-1.042/doc/guides/9_customYoctoVersions.md). \n\n\n\u003cbr\u003e\n\n# Author\n* *[rsyocto GmbH \u0026 Co. KG](https://rsyocto.com/)*; **Robin Sebastian,M.Sc. [(LinkedIn)](https://www.linkedin.com/in/robin-sebastian-a5080220a)**\n\n**For commercial users, please visit the *rsyocto* embedded service provider website:** \n[**rsyocto.com**](https://rsyocto.com/)\n\n\n[![Gitter](https://badges.gitter.im/rsyocto/community.svg)](https://gitter.im/rsyocto/community?utm_source=badge\u0026utm_medium=badge\u0026utm_campaign=pr-badge)\n[![Email me!](https://img.shields.io/badge/Ask%20me-anything-1abc9c.svg)](mailto:git@robseb.de)\n\n[![GitHub stars](https://img.shields.io/github/stars/robseb/meta-intelfpga?style=social)](https://GitHub.com/robseb/meta-altera/stargazers/)\n[![GitHub watchers](https://img.shields.io/github/watchers/robseb/meta-intelfpga?style=social)](https://github.com/robseb/meta-altera/watchers)\n[![GitHub followers](https://img.shields.io/github/followers/robseb?style=social)](https://github.com/robseb)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frobseb%2Fmeta-intelfpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frobseb%2Fmeta-intelfpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frobseb%2Fmeta-intelfpga/lists"}