{"id":18870501,"url":"https://github.com/robseb/rstools","last_synced_at":"2026-02-14T19:30:13.983Z","repository":{"id":240748090,"uuid":"465681625","full_name":"robseb/rstools","owner":"robseb","description":"Intel (ALTERA) SoC FPGA Developmnet Tools for acessing the FPGA Manager, Soft-IP ... with Linux","archived":false,"fork":false,"pushed_at":"2024-06-03T14:25:32.000Z","size":2434,"stargazers_count":0,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"main","last_synced_at":"2024-12-30T23:48:12.841Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/robseb.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-03-03T10:57:50.000Z","updated_at":"2024-06-03T14:25:36.000Z","dependencies_parsed_at":"2024-05-20T19:28:10.024Z","dependency_job_id":null,"html_url":"https://github.com/robseb/rstools","commit_stats":null,"previous_names":["robseb/rstools"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/robseb%2Frstools","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/robseb%2Frstools/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/robseb%2Frstools/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/robseb%2Frstools/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/robseb","download_url":"https://codeload.github.com/robseb/rstools/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":239816759,"owners_count":19701802,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-08T05:20:56.330Z","updated_at":"2026-02-14T19:30:13.927Z","avatar_url":"https://github.com/robseb.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# rstools\n Intel (ALTERA) SoC FPGA Developmnet Tools for acessing the FPGA Manager, Soft-IP ... with Linux\n\n\n`meta-intelfpga` is a BSP-Layer for bringing support for *Intel* (*ALTERA*) SoC-FPGAs (*SoCFPGAs*) to the *Yocto Project*.\nThe *socfpgatools* add a simple way for fully accessing the FPGA Manager of the Intel (*ALTERA*) Cyclone V SoC-FPGA (*SoCFPGA*).\n\nAdditionally, with a single command it is possible to read or write the *ARM AXI-Bridge* (*Lightweight HPS-to-FPGA-* (*LWHPS2FPGA*) or *HPS-to-FPGA (*HPS2FPGA*) Bridge*) to the FPGA Fabric.\nIt enables to check the startus of the FPGA Fabric, write or read any address of the MPU (*HPS*) Memory space or the read and write the general purpose in- (*GPI*) and output- (*GPO*) registers. \n\nThis source code and the [*meta-intelfpga*](https://github.com/robseb/meta-intelfpga) is a part of my [*rsyocto*](https://github.com/robseb/rsyocto). A embedded Linux Distribution for *Intel* SoC-FPGAs.\n\nDies ist ein Test \n\n\u003cbr\u003e\n\n___\n## Features \n\n* **The layer adds following features to the final Linux command set:**\n  *  **FPGA Status**\n      * Reading the Status of the FPGA fabric \n      ````bash\n      FPGA-status \n      ````\n      * Help- and Info- Output with the suffix `-h` \n        ````bash\n          Command to read current Status mode of the FPGA fabric\n          FPGA-status\n                  read the status with detailed output\n          FPGA-status -d\n                  POWER UP:        0\n                  RESET:           1\n                  CONFIG:          2\n                  INIT:            3\n                  USER:            4\n                  UNKNOWN:         5\n        ````\n  * **FPGA Configuration Mode / MSEL** \n    * Reading the Configuration mode of the FPGA (selected with the MSEL-Bit Switch)\n        ````bash\n        FPGA-status\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n           ````bash\n          Command to read the selected FPGA configuration mode.\n          This is set with the MSEL-Switch.\n          FPGA-readMSEL\n                  read MSEL with detailed output\n          FPGA-readMSEL -d\n                  read MSEL as decimal value\n          ````\n * **FPGA Fabric Reset** \n    * Resetting the FPGA fabric (remove the running configuration)\n        ````bash\n        FPGA-resetFabric\n        ````\n     * Help output with the suffix `-h`  \n          ````bash\n          Command to reset the FPGA fabic\n          A reset clears the current configuration\n          of the FPGA fabric\n          After a reset is the FPGA in the RESET Mode\n          FPGA-resetFabric -r\n                  reset the FPGA with detailed output\n          FPGA-status -d\n                  read the status as decimal value\n                  0 =\u003e ERROR: Resting of the FPGA failed!\n                  1 =\u003e Success: FPGA config is deleted\n          ````\n  * **Write FPGA Configuration** \n    * Writing a new FPGA configuration\n        ````bash\n        FPGA-writeConfig\n        ````\n     * Help output with the suffix `-h`  \n          ````bash\n            Command to change the FPGA fabric configuration\n            for Cyclone V use following RBF (.rbf) config file settings\n            MSEL=00100: PP16 with no AES and no Data compression\n            MSEL=00101: PP16 with AES and no Data compression\n            FPGA-writeConfig -f [config rbf file path] {-b [optional]}\n                    change the FPGA config with a selected .rbf file\n            FPGA-writeConfig -r {-b [optional]}\n                    restore to the boot up FPGA configuration\n                    this conf File is located: /usr/rsyocto/running_bootloader_fpgaconfig.rbf\n                    suffix: -b -\u003e only decimal result output\n                                                    Error:  0\n                                                    Succses:1\n          ````\n      * Required MSEL-Bit Switch Selection to allow Linux to change the FPGA configuration:\n        * `MSEL= 00100`: Passive parallel x16 with no AES and Data compression\n        * `MSEL= 00101`: Passive parallel x16  with AES and Data compression\n\n * **LWHPS2FPGA-, HPS2FPGA-Bridge or MPU address space read** \n    * Reading a address (*32-Bit* register) of the *HPS-to-FPGA-*, *Lightweight-HPS-to-FPGA- Bridge* or from the *MPU* (*HPS*) memory space interface\n        ````bash\n        FPGA-readBridge\n        ````\n     * Help output with the suffix `-h`  \n        ````bash\n        -------------------------------------------------------------------------------------\n        |\tCommand to read a 32-bit register of a HPS-to-FPGA Bridge\t            |\n        |\t\tor of the entire MPU (HPS) Memory space\t\t\t\t    |\n        |  Note: Be sure that the bridge to read is enabled within the Platform Designer    |\n        -------------------------------------------------------------------------------------\n        |$\tFPGA-readBridge -lw [offset address in hex]\t\t\t\t\t\n        |\t\tread a 32-bit register of the Lightweight HPS-to-FPGA Bridge\t\t\n        |\t\te.g.: FPGA-readBridge -lw 0A\t\t\t\t\t\t\t\n        |$\tFPGA-readBridge -hf [offset address in hex]\t\t\t\t\n        |\t\tread a 32-bit register of the HPS-to-FPGA AXI Bridge\t\n        |\t\te.g.: FPGA-readBridge -hf 8C\t\t\t\t\t\t\t\n        |$\tFPGA-readBridge -mpu [module address in hex]\n        |\t\tread a 32-bit register for the entire MPU (HPS) memory space\n        |\t\te.g.: FPGA-readBridge -mpu 87\n        |\t\tSuffix: -b -\u003e only decimal result output\n        |\t\tSuffix: -r -\u003e Auto refrech the value for 15sec\n        |$\tFPGA-readBridge -lw|hf|mpu| \u003coffset address in hex\u003e -b|r\n        -------------------------------------------------------------------------------------\n        ````\n * **LWHPS2FPGA-, HPS2FPGA-Bridge or MPU address space Read** \n    * * Writing to a address (*32-Bit* register) of the *HPS-to-FPGA-*, *Lightweight-HPS-to-FPGA- Bridge* or from the *MPU* (*HPS*) memory space interface\n        ````bash\n        FPGA-writeBridge\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n        ````bash\n        -------------------------------------------------------------------------------------\n        |\tCommand to write to a 32-bit register of a HPS-to-FPGA Bridge\t            |\n        |\t\tor of the entire MPU (HPS) Memory space\t\t\t\t    |\n        |  Note: Be sure that the bridge to write is enabled within the Platform Designer   |\n        -------------------------------------------------------------------------------------\n        |$\tFPGA-writeBridge -lw [offset address in hex] [value in dec]\t\t\t\t\t\n        |\t\twrite to a 32-bit register of the Lightweight HPS-to-FPGA Bridge in dec\t\n        |\t\te.g.: FPGA-writeBridge -lw 0A 10\t\t\t\t\t\t\n        |$\tFPGA-writeBridge -lw [offset address in hex] -h [value in hex]\t\t\t\n        |\t\twrite to a 32-bit register of the Lightweight HPS-to-FPGA Bridge in hex\t\t\n        |\t\te.g.: FPGA-writeBridge -lw 0A -h 12\t\t\t\t\t\t\n        |$\tFPGA-writeBridge -lw [offset address in hex] -b [bit pos] [bit value] \n        |\t\tset a bit of the Lightweight HPS-to-FPGA Bridge\t\t\n        |\t\te.g.: FPGA-writeBridge -lw 0A -b 3 1\t\t\t\t\t\t\n        |$\tFPGA-writeBridge -hf [offset address in hex] [value dec]\t\t\t\t\n        |\t\twrite to a 32-bit register of the HPS-to-FPGA AXI Bridge\t\n        |\t\te.g.: FPGA-writeBridge -hf 8C\t\t\t\t\t\t\t\n        |$\tFPGA-writeBridge -mpu [module address in hex] [value dec]\n        |\t\twrite to a 32-bit register for the entire MPU (HPS) memory space\n        |\t\te.g.: FPGA-writeBridge -mpu 87\n        |\t\tSuffix: -b -\u003e only decimal result output\n        |$\tFPGA-writeBridge -lw|hf|mpu| \u003coffset address in hex\u003e -h|-b|\u003cvalue dec\u003e \u003cvalue hex\u003e|\u003cbit pos\u003e \u003cbit value\u003e  -b\n        -------------------------------------------------------------------------------------\n        ````\n* **GPI Register Read (*GPI*)** \n    * Reading the 32-Bit direct access Register (*written by the FPGA*)\n        ````bash\n        FPGA-gpiRead\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n        ````bash\n             Command to read general-purpose input signals (gpi) from\n             the FPGA fabric.\n             The FPGA can set the 32 Bit gpi (input) register\n              FPGA-gpiRead\n                      read gpi with detailed output\n              FPGA-gpiRead -d\n                      read gpi as decimal value\n         ````\n* **GPO Register Write (*GPO*)** \n    * Writing the 32-Bit direct access Register to the FPGA\n        ````bash\n        FPGA-gpoWrite\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n        ````bash\n               Command to write the general-purpose output signals (gpo) to\n              the FPGA fabric\n              The HPS get write a 32 Bit register to the FPGA\n              FPGA-gpoWrite -h [uint]\n                      writing the whole 32 Bit gpo as HEX\n                      e.g.: FPGA-gpoWrite -h ffffffff\n              FPGA-gpoWrite -d [uint]\n                      writing the whole 32 Bit gpo as DEC\n                      e.g.: FPGA-gpoWrite -d 12345\n              FPGA-gpoWrite -b [bit pos] [value]\n                      writing a specific Bit position\n                      e.g.: FPGA-gpoWrite -b 16 1\n                                (to set the Bit 16 of the gpo Regiser)\n         ````\n ### For more informations and examples about the usage of these commands please follow the [*rsYocto*](https://github.com/robseb/rsyocto) documentation. \n \u003cbr\u003e\n        \n\n## Using this Code \nThe Code was writen with **Microsoft Visual Studio 2019 with Linux Development for C++** and as target [*rsYocto*](https://github.com/robseb/rsyocto) used. \nFor informations how to use Microsoft Visual Studio 2019 for embedded Linux development please follow the [*rsYocto*](https://github.com/robseb/rsyocto) documentation.\n\n\n\u003cbr\u003e\n\n# Author\n* **Robin Sebastian**\n\n*rstools*  and *meta-intelfpa* are projects, that I have fully developed on my own. No companies are involved in my projects. \nI’m recently graduated as a master in electrical engineering with the major embedded systems (M. Sc.).\n\n[![Gitter](https://badges.gitter.im/rsyocto/community.svg)](https://gitter.im/rsyocto/community?utm_source=badge\u0026utm_medium=badge\u0026utm_campaign=pr-badge)\n[![Email me!](https://img.shields.io/badge/Ask%20me-anything-1abc9c.svg)](mailto:git@robseb.de)\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frobseb%2Frstools","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frobseb%2Frstools","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frobseb%2Frstools/lists"}