{"id":18870506,"url":"https://github.com/robseb/rstoolsa10","last_synced_at":"2025-10-05T23:06:57.861Z","repository":{"id":240748099,"uuid":"228671308","full_name":"robseb/rstoolsA10","owner":"robseb","description":"Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA 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rstoolsA10\n\n **`rstoolsA10`is the source code of  [*meta-rstools*](https://github.com/robseb/meta-rstools).**\n\n`meta-rstools` is a Layer for the Yocto project to add a simple way for fully accessing the FPGA Manager of the Intel (ALTERA) Arria 10 SoC-FPGA (SoCFPGA).\n\nWith a single command it is possible to change FPGA configuration or to read and write the *ARM AXI-Bridge* to the FPGA fabric. \nThe layer is a part of [*rsYocto*](https://github.com/robseb/rsyocto).\n\n`Note: The Writing FPGA Fabric Feature is under development!`\n\n\n___\n## Features \n\n* **The layer adds following features to the final Linux command set:**\n  *  **FPGA Status**\n      * Reading the Status of the FPGA fabric \n      ````bash\n      FPGA-status \n      ````\n      * Help- and Info- Output with the suffix `-h` \n        ````bash\n          Command to read current Status mode of the FPGA fabric\n          FPGA-status\n                  read the status with detailed output\n          FPGA-status -d\n                  POWER UP:        0\n                  RESET:           1\n                  CONFIG:          2\n                  INIT:            3\n                  USER:            4\n                  UNKNOWN:         5\n        ````\n  * **FPGA Configuration Mode / MSEL** \n    * Reading the Configuration mode of the FPGA (selected with the MSEL-Bit Switch)\n        ````bash\n        FPGA-status\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n          ````bash\n          Command to read the selected FPGA configuration mode.\n          This is set with the MSEL-Switch.\n          FPGA-readMSEL\n                  read MSEL with detailed output\n          FPGA-readMSEL -d\n                  read MSEL as decimal value\n          ````\n * **FPGA Fabric Reset** \n    * Resetting the FPGA fabric (remove the running configuration)\n        ````bash\n        FPGA-resetFabric\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n          ````bash\n          Command to reset the FPGA fabic\n          A reset clears the current configuration\n          of the FPGA fabric\n          After a reset is the FPGA in the RESET Mode\n          FPGA-resetFabric -r\n                  reset the FPGA with detailed output\n          FPGA-status -d\n                  read the status as decimal value\n                  0 =\u003e ERROR: Resting of the FPGA failed!\n                  1 =\u003e Success: FPGA config is deleted\n          ````\n  * **Write FPGA Configuration** \n    * Writing a new FPGA configuration\n        ````bash\n        FPGA-writeConfig\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n          ````bash\n            Command to change the FPGA fabric configuration\n            for Cyclone V use following RBF (.rbf) Config File Setings\n            MSEL=00100: PP16 with no AES and no Data compression\n            MSEL=00101: PP16 with AES and no Data compression\n            FPGA-writeConfig -f [config rbf file path] {-b [optinal]}\n                    change the FPGA config with a selected .rbf file\n            FPGA-writeConfig -r {-b [optinal]}\n                    restore to the boot up FPGA configuration\n                    this Conf File is located: /usr/rsyocto/running_bootloader_fpgaconfig.rbf\n                    suffix: -b -\u003e only decimal result output\n                                                    Error:  0\n                                                    Succses:1\n          ````\n      * Required MSEL-Bit Switch Selection to allow Linux to change the FPGA configuration:\n        * `MSEL= 00100`: Passive parallel x16 with no AES and Data compression\n        * `MSEL= 00101`: Passive parallel x16  with AES and Data compression\n\n * **AVALON/AXI Bridge Read** \n    * Reading a Address (32 Bit register) of the HPS-to-FPGA- or Lightweight-HPS-to-FPGA Bridge interface\n        ````bash\n        FPGA-readBridge\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n        ````bash\n          read a register on the Lightweight HPS-FPGA Brige\n                e.g.: FPGA-readBridge -lw 0a\n\n          FPGA-readBridge -hf [offset module address hex]\n                read a register on the HPS to FPGA AXI Bridge\n                e.g.: FPGA-readBridge -lw 0a\n\n                suffix: -b -\u003e only decimal result output\n         ````\n* **AVALON/AXI Bridge Write** \n    * Writing a 32 Bit Value to the HPS-to-FPGA- or Lightweight-HPS-to-FPGA Bridge interface\n        ````bash\n        FPGA-writeBridge\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n        ````bash\n          Command write to address of a HPS-FPGA Bridge\n          address\n          FPGA-readBridge -lw [offset module address hex]\n                  read the register on the Lightweight HPS-FPGA Brige\n                  e.g.: FPGA-writeBridge -lw 0a\n\n          FPGA-writeBridge -hf [offset module address hex] [value dec]\n                  write to the HPS to FPGA AXI Bridge Interface with a dec values\n                  e.g.: FPGA-writeBridge -hf 0a 255\n          FPGA-writeBridge -hf [offset module address hex] -h [value hex]\n                  write to the HPS to FPGA AXI Bridge Interface with a hex values\n                  e.g.: FPGA-writeBridge -hf 0a -h ff\n          FPGA-writeBridge -hf [offset module address hex] -b [Bit pos] [value]\n                  Set or Reset a Bit on HPS to FPGA AXI Bridge register\n                  e.g.: FPGA-writeBridge -hf 0a -b 8 0\n\n                  suffix: -b -\u003e only decimal result output\n                                                  Error:  0\n                                                  Succses:1\n         ````\n* **GPI Register Read** \n    * Reading the 32 Bit direct access Register (written by the FPGA)\n        ````bash\n        FPGA-gpiRead\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n        ````bash\n             Command to read general-purpose input signals (gpi) from\n             the FPGA fabric.\n             The FPGA can set the 32 Bit gpi (input) register\n              FPGA-gpiRead\n                      read gpi with detailed output\n              FPGA-gpiRead -d\n                      read gpi as decimal value\n         ````\n* **GPO Register Write** \n    * Writing the 32 Bit direct access Register to the FPGA\n        ````bash\n        FPGA-gpoWrite\n        ````\n     * Help- and Info- Output with the suffix `-h`  \n        ````bash\n               Command to write the general-purpose output signals (gpo) to\n              the FPGA fabric\n              The HPS get write a 32 Bit register to the FPGA\n              FPGA-gpoWrite -h [uint]\n                      writing the whole 32 Bit gpo as HEX\n                      e.g.: FPGA-gpoWrite -h ffffffff\n              FPGA-gpoWrite -d [uint]\n                      writing the whole 32 Bit gpo as DEC\n                      e.g.: FPGA-gpoWrite -d 12345\n              FPGA-gpoWrite -b [bit pos] [value]\n                      writing a specific Bit position\n                      e.g.: FPGA-gpoWrite -b 16 1\n                                (to set the Bit 16 of the gpo Regiser)\n         ````\n ### For more informations and examples about the usage of these commands please follow the [*rsYocto*](https://github.com/robseb/rsyocto) documentation. \n \u003cbr\u003e\n        \n\n## Using this Code \nThe Code was writen with **Microsoft Visual Studio 2019 with Linux Development for C++** and as target [*rsYocto*](https://github.com/robseb/rsyocto) used. \nFor informations how to use Microsoft Visual Studio 2019 for embedded Linux development please follow the [*rsYocto*](https://github.com/robseb/rsyocto) documentation.\n\n\n\u003cbr\u003e\n\n# Author\n* *rsyocto*; **Robin Sebastian,M.Sc. [(LinkedIn)](https://www.linkedin.com/in/robin-sebastian-a5080220a)**\n\n*rstoolsA10* and *rsyocto* are a self-developed projects in which no other companies are involved. \nIt is specifically designed to serve students and the Linux/FPGA open-source community with its publication on GitHub and its open-source MIT license. \nIn the future, *rsyocto* will retain its open-source status and it will be further developed. \n\nDue to the enthusiasm of commercial users, special features for industrial, scientific and automotive applications \nwere developed and ready for the implementation in a highly optimazed closed commercial version. \nPartnerships as an embedded SoC-FPGA design service to fulfil these specific commercial requirements are offered. \nIt should help, besides students with the *rsyocto* open-source version, commercial users, as well.   \n\n**For commercial users, please visit the *rsyocto* embedded service provider website:** \n[**rsyocto.com**](https://rsyocto.com/)\n\n[![Gitter](https://badges.gitter.im/rsyocto/community.svg)](https://gitter.im/rsyocto/community?utm_source=badge\u0026utm_medium=badge\u0026utm_campaign=pr-badge)\n[![Email me!](https://img.shields.io/badge/Ask%20me-anything-1abc9c.svg)](mailto:git@robseb.de)\n\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frobseb%2Frstoolsa10","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frobseb%2Frstoolsa10","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frobseb%2Frstoolsa10/lists"}