{"id":37080049,"url":"https://github.com/rpm2003rpm/vagen","last_synced_at":"2026-01-14T09:42:51.013Z","repository":{"id":81311688,"uuid":"605641263","full_name":"rpm2003rpm/vagen","owner":"rpm2003rpm","description":"Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)","archived":false,"fork":false,"pushed_at":"2025-02-28T19:48:30.000Z","size":1679,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-11-28T11:08:24.687Z","etag":null,"topics":["cadence","cadence-virtuoso","generator","simulation","testbench","testbench-generator","verilog-a","verilog-ams","veriloga","waveform","waveform-generator"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rpm2003rpm.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-02-23T15:36:22.000Z","updated_at":"2025-08-08T00:59:00.000Z","dependencies_parsed_at":null,"dependency_job_id":"4a618f72-2a3d-424c-9351-c47b992234ee","html_url":"https://github.com/rpm2003rpm/vagen","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/rpm2003rpm/vagen","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rpm2003rpm%2Fvagen","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rpm2003rpm%2Fvagen/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rpm2003rpm%2Fvagen/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rpm2003rpm%2Fvagen/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rpm2003rpm","download_url":"https://codeload.github.com/rpm2003rpm/vagen/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rpm2003rpm%2Fvagen/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28416120,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-14T08:38:59.149Z","status":"ssl_error","status_checked_at":"2026-01-14T08:38:43.588Z","response_time":107,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cadence","cadence-virtuoso","generator","simulation","testbench","testbench-generator","verilog-a","verilog-ams","veriloga","waveform","waveform-generator"],"created_at":"2026-01-14T09:42:50.457Z","updated_at":"2026-01-14T09:42:50.997Z","avatar_url":"https://github.com/rpm2003rpm.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# vagen\n\n## What is vagen?\n\nvagen was created mainly to generate verilogA stimulus for verification of complex analog IPs. However, it has wrappers for most of the verilogA reserved words, so it also generates verilogA models.\n\n## Instalation \n\nYou can install vagen by typing the command:\n\n```\n    pip3 install vagen\n```\n\n## Example 1: Stimulus for verification of a DCDC\n\nLet's assume that a stimulus with the following sequence is required:\n\n* VDD must rise from 0 to 5.0V in 10us.\n* After 10us, the clock signal (CLK) must start with a frequency of 4MHz. CLK domain is VDD.\n* After 1us, RST must rise. RST domain is VDD.\n* Wait for the positive edge of the READY signal. READY domain is VDD. \n* A current of 100mA must be drawn from the in OUT with a rise time of 100ns. \n* After 10us, the bus CONFIG_VOUT[3:0] must be changed from 0 to 5. CONFIG_VOUT[3:0] domain is VDD.\n* After 20us, finishes the simulation. \n\nThe python code that generates this stimulus is shown below:\n\n```\nimport vagen as va\n\n#Create a module     \nmod = va.HiLevelMod(\"DCDC_STML\")\n\n#Create pins\nVDD = mod.vdc(name = \"VDD\", width = 1, direction = \"inout\")\nOUT = mod.idc(name = \"OUT\", width = 1, direction = \"inout\")\nCLK = mod.clock(mod.dig(name = \"CLK\", domain = VDD, width = 1, direction = \"output\", rise = 100e-12, fall = 100e-12))\nRST = mod.dig(name = \"RST\", domain = VDD, width = 1, value = 0, direction = \"output\", rise = 100e-12, fall = 100e-12)\nREADY = mod.dig(name = \"READY\", domain = VDD, width = 1, direction = \"input\")\nCONFIG_VOUT = mod.dig(name = \"CONFIG_VOUT\", domain = VDD, width = 4, value = 0, direction = \"output\", rise = 100e-12, fall = 100e-12)\n\n#READY positive event\nEVNT_READY = va.Cross(READY.diffHalfDomain, \"rising\")\n\n#Sequence\nmod.seq(True)(\n    VDD.setRiseFall(10e-6, 10e-6),\n    VDD.applyV(5.0),\n    va.WaitUs(10), \n    CLK.on(4e6),\n    va.WaitUs(1),\n    RST.write(True),\n    va.WaitSignal(EVNT_READY),\n    OUT.setRiseFall(100e-9, 100e-9),\n    OUT.applyI(100e-3), #Positive current enters the model\n    va.WaitUs(10),\n    CONFIG_VOUT.write(5),\n    va.WaitUs(20),\n    va.Finish()\n)\n\n#Save veriloga file\nfile = open('veriloga.va', 'w')\nfile.write(mod.getVA())\nfile.close()\n```\n\n## Example 2: More than one sequence in the same veriloga\n\nYou can create a veriloga parameter called testSeq\n\n```\nseqPar = mod.par(name = \"testSeq\", value = 0)\n```\n\nAnd then use this parameter to select the sequence depending on the value\n\n```\n#sequence 1 \nmod.seq(seqPar == 1)(\n...\n)\n\n#sequence 2\nmod.seq(seqPar == 2)(\n...\n)\n```\n\n## Example 3: Model of a configurable resistor\n\nAs mentioned before, vagen can be used to generate models. As an example, the code below generates a veriloga model of a configurable resistor.\n\n```\nimport vagen as va\n\n#Create a module\nmod = va.HiLevelMod(\"CONFIG_RES\")\n\n#Create pins\nVDD = mod.electrical(name = \"VDD\", width = 1, direction = \"inout\")\nIN1 = mod.electrical(name = \"IN1\", width = 1, direction = \"inout\")\nIN2 = mod.electrical(name = \"IN2\", width = 1, direction = \"inout\")\nCONFIG = mod.dig(name = \"CONFIG\", domain = VDD, width = 4, inCap = 100e-15, direction = \"input\")\n\n#Parameters\nalfa = mod.par(name = \"alfa\", value = 10.0)\n\n#Analog block\nmod.analog(\n    va.Branch(IN1, IN2).vCont(va.Branch(IN1, IN2).i*(va.Real(CONFIG.read(signed = False)) + 1)*alfa)\n)\n\n#Save veriloga file\nfile = open('veriloga.va', 'w')\nfile.write(mod.getVA())\nfile.close()\n```\n\n# More examples\nExtra examples will be added to examples folder\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frpm2003rpm%2Fvagen","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frpm2003rpm%2Fvagen","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frpm2003rpm%2Fvagen/lists"}