{"id":13423286,"url":"https://github.com/rust-embedded/riscv","last_synced_at":"2025-09-24T16:18:58.461Z","repository":{"id":33810495,"uuid":"104085299","full_name":"rust-embedded/riscv","owner":"rust-embedded","description":"Low level access to RISC-V processors","archived":false,"fork":false,"pushed_at":"2025-04-21T16:50:19.000Z","size":1346,"stargazers_count":932,"open_issues_count":12,"forks_count":168,"subscribers_count":32,"default_branch":"master","last_synced_at":"2025-04-21T17:43:39.840Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/rust-embedded.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":"CODE_OF_CONDUCT.md","threat_model":null,"audit":null,"citation":null,"codeowners":".github/CODEOWNERS","security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2017-09-19T14:24:48.000Z","updated_at":"2025-04-21T12:38:27.000Z","dependencies_parsed_at":"2023-10-11T14:44:28.553Z","dependency_job_id":"799939bf-0d09-4513-8405-f31f719f8914","html_url":"https://github.com/rust-embedded/riscv","commit_stats":{"total_commits":238,"total_committers":37,"mean_commits":"6.4324324324324325","dds":0.6764705882352942,"last_synced_commit":"ec99d035d62abaf2e6053c263e8a58a1186d1bbd"},"previous_names":["riscv-rust/riscv"],"tags_count":18,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rust-embedded%2Friscv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rust-embedded%2Friscv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rust-embedded%2Friscv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rust-embedded%2Friscv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/rust-embedded","download_url":"https://codeload.github.com/rust-embedded/riscv/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250514756,"owners_count":21443208,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-07-31T00:00:27.912Z","updated_at":"2025-09-24T16:18:58.387Z","avatar_url":"https://github.com/rust-embedded.png","language":"Rust","readme":"# RISC-V crates\n\nThis repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:\n\n* [`riscv`]: CPU registers access and intrinsics\n* [`riscv-pac`]: Common traits to be implemented by RISC-V PACs\n* [`riscv-peripheral`]: Interfaces for standard RISC-V peripherals\n* [`riscv-rt`]: Startup code and interrupt handling\n* [`riscv-semihosting`]: Semihosting for RISC-V processors\n* [`riscv-target-parser`]: Utility crate for parsing RISC-V targets in build scripts\n\nThis project is developed and maintained by the [RISC-V team][team].\n\n### Contribution\n\nUnless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the\nwork by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any\nadditional terms or conditions.\n\n## Code of Conduct\n\nContribution to this crate is organized under the terms of the [Rust Code of\nConduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises\nto intervene to uphold that code of conduct.\n\n[`riscv`]: https://crates.io/crates/riscv\n[`riscv-pac`]: https://crates.io/crates/riscv-pac\n[`riscv-peripheral`]: https://crates.io/crates/riscv-peripheral\n[`riscv-rt`]: https://crates.io/crates/riscv-rt\n[`riscv-semihosting`]: https://crates.io/crates/riscv-semihosting\n[`riscv-target-parser`]: https://crates.io/crates/riscv-target-parser\n[team]: https://github.com/rust-embedded/wg#the-risc-v-team\n[CoC]: CODE_OF_CONDUCT.md\n","funding_links":[],"categories":["Architecture support crates","Rust"],"sub_categories":["RISC-V"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frust-embedded%2Friscv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Frust-embedded%2Friscv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Frust-embedded%2Friscv/lists"}