{"id":19701472,"url":"https://github.com/sadegh15khedry/vhdl-projects","last_synced_at":"2025-02-27T12:46:47.686Z","repository":{"id":243058028,"uuid":"407021909","full_name":"sadegh15khedry/VHDL-Projects","owner":"sadegh15khedry","description":"This repository contains various VHDL projects showcasing digital logic circuits implemented using VHDL.","archived":false,"fork":false,"pushed_at":"2024-06-06T12:43:59.000Z","size":1306,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-01-10T10:58:21.134Z","etag":null,"topics":["and-gate","c","logical-gates","nand-gate","or-gate","vhdl-code","xor-gate"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/sadegh15khedry.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-09-16T04:40:25.000Z","updated_at":"2024-07-03T15:35:15.000Z","dependencies_parsed_at":"2024-06-06T13:55:33.354Z","dependency_job_id":"3a8d120a-18ae-4951-9e67-ef2d6fbf5c09","html_url":"https://github.com/sadegh15khedry/VHDL-Projects","commit_stats":null,"previous_names":["sadegh15khedry/vhdlprojects","sadegh15khedry/vhdl-projects"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sadegh15khedry%2FVHDL-Projects","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sadegh15khedry%2FVHDL-Projects/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sadegh15khedry%2FVHDL-Projects/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sadegh15khedry%2FVHDL-Projects/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/sadegh15khedry","download_url":"https://codeload.github.com/sadegh15khedry/VHDL-Projects/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241014943,"owners_count":19894328,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["and-gate","c","logical-gates","nand-gate","or-gate","vhdl-code","xor-gate"],"created_at":"2024-11-11T21:09:07.140Z","updated_at":"2025-02-27T12:46:47.663Z","avatar_url":"https://github.com/sadegh15khedry.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# VHDL Projects\n\nThis repository contains various VHDL projects showcasing digital logic circuits implemented using VHDL.\n\n## Projects\n\n1. [NAND NAND Logic](https://github.com/sadegh15khedry/VHDLProjects/tree/master/NAND_NAND_Logic): Implements a digital logic circuit using NAND gates.\n2. [NAND OR Negation Logic](https://github.com/sadegh15khedry/VHDLProjects/tree/master/NAND_OR_Negation_Logic): Implements a digital logic circuit using NAND, OR, and NOT gates.\n3. [XOR AND Gate Simulator](https://github.com/sadegh15khedry/VHDLProjects/tree/master/XOR_AND_Gate_Simulator): Simulates the behavior of XOR and AND gates.\n4. [NAND Gate](https://github.com/sadegh15khedry/VHDLProjects/tree/master/nand): Implements a digital logic circuit using NAND gates.\n5. [OR Gate](https://github.com/sadegh15khedry/VHDLProjects/tree/master/or): Implements a digital logic circuit using OR gates.\n\nEach project contains VHDL code for the corresponding digital logic circuit along with testbench files to verify functionality.\n\n## License\n\nThis repository is licensed under the MIT License - see the [LICENSE](LICENSE) file for details.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsadegh15khedry%2Fvhdl-projects","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsadegh15khedry%2Fvhdl-projects","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsadegh15khedry%2Fvhdl-projects/lists"}