{"id":25084657,"url":"https://github.com/salekinsirajus/riscvassembler","last_synced_at":"2026-05-03T06:36:08.305Z","repository":{"id":260851294,"uuid":"839889497","full_name":"salekinsirajus/riscvassembler","owner":"salekinsirajus","description":"risc-v assembler, currently supports 32bit base integer for linux","archived":false,"fork":false,"pushed_at":"2026-03-13T02:05:35.000Z","size":146,"stargazers_count":3,"open_issues_count":2,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2026-03-13T09:06:25.417Z","etag":null,"topics":["assembler","hacking","risc-v","risc-v-assembly","riscv-assembler"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/salekinsirajus.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2024-08-08T14:26:28.000Z","updated_at":"2026-03-13T02:05:39.000Z","dependencies_parsed_at":null,"dependency_job_id":"01f64ffe-1800-4b3d-a4b2-a77262509d13","html_url":"https://github.com/salekinsirajus/riscvassembler","commit_stats":null,"previous_names":["salekinsirajus/risc-v-assembler","salekinsirajus/riscvassembler"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/salekinsirajus/riscvassembler","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/salekinsirajus%2Friscvassembler","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/salekinsirajus%2Friscvassembler/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/salekinsirajus%2Friscvassembler/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/salekinsirajus%2Friscvassembler/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/salekinsirajus","download_url":"https://codeload.github.com/salekinsirajus/riscvassembler/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/salekinsirajus%2Friscvassembler/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":32560838,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-03T03:21:47.309Z","status":"ssl_error","status_checked_at":"2026-05-03T03:21:43.884Z","response_time":103,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembler","hacking","risc-v","risc-v-assembly","riscv-assembler"],"created_at":"2025-02-07T07:18:03.106Z","updated_at":"2026-05-03T06:36:08.299Z","avatar_url":"https://github.com/salekinsirajus.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISC-V Assembler\nA reference assembler for RISC-V backend. Primarily for learning\nand hacking. Implements the grammar described in the \n[riscv-asm-manual](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc).\nELF spec reference is [here](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc).\n\n## How to build\nMake sure `flex` and `bison` are present in your system.\n```\nmake\n```\n## How to run\nThe test files are under `tests`. Once the build is made,\nuse one of the assembly files from there to generate an\nobject file.\n```\n./riscvass tests/helloworld.s\n```\n\nThis will result in an object file called `out.o`. you\ncan open it with a hex viewer like `xxd out.o` to see\nthe content.\n\n## Work in progress\n- [x] initialize symbol table and string table\n- [x] add entry to the strtab\n- [x] proper offset calculation for section headers\n- [x] add entry to the symtab\n- [x] add instructions to the text section\n- [x] address/ref resolution (single pass.)\n- [x] Expand lexer to recognize all registers x0-x31 \n- [x] Get lexer to recongize all aliases (t0-t6, s0-s11, a0-a7)\n- [x] Implement alias recognition for commonly used registers (ra, sp, gp, tp)\n- [x] Extend immediate parsing to support negative numbers, hexadecimal (0x...), binary (0b...), and larger constants.\n- [x] Implement the ability to add custom output filename\n- [x] Fix the offsets (sign-extension, alignment, rang-check) outside the emit functions\n- [ ] Implement a deserialize function for J-type\n- [ ] Implement label/symbol visibility\n- [ ] Add unresolved symbols to rela.text \n- [ ] implement full RV32I instruction coverage (LUI, AUIPC, JALR, all arithmetic, shifts, branches, loads/stores).\n- [ ] Implement proper pseudo-instruction expansion to multiple actual instructions (e.g., LI → LUI+ADDI).\n- [ ] Implement .bss section with proper ELF flags and handling of uninitialized data.\n- [ ] Implement .rodata section for read-only data\n- [ ] Implement .word, .byte, .half, .long directives for data initialization.\n- [ ] Implement .align directive for section alignment.\n- [ ] Implement .comm and .size directives.\n- [ ] Implement .equ/.set directives for defining constants.\n- [ ] Extend label handling to support multiple sections (text, data, rodata, bss).\n- [ ] Implement pseudo-instructions: LI, LA, NEG, NOT, SEQZ, SNEZ, SGTZ, etc.\n- [ ] Implement macro (?)\n- [ ] Update ELF header fields dynamically: e_shnum, e_shstrndx, e_shoff, and section flags.\n- [ ] Implement arithmetic expressions for immediates and label offsets.\n- [ ] Implement proper handling of global vs local symbols in the symbol table.\n- [x] Improve error handling with line numbers, semantic checks\n- [ ] Improve error handling with warnings for undefined symbols.\n- [ ] Add logging/debugging support for unresolved instructions and symbol resolution.\n- [ ] Refactor error reporting/debug mode with multiple output streams so they can be turned on or off as needed\n- [ ] add a test suite and example output files\n- [ ] Implement ECALL and system instruction handling fully with proper encoding.\n- [ ] Add support for forward-declared labels in data sections.\n- [ ] Refactor ELF32 serialization to correctly update offsets, sizes, and section headers dynamically.\n- [ ] verify proper handling of branch offsets for B-type and J-type instructions.\n- [ ] Add support for effectively required extensions\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsalekinsirajus%2Friscvassembler","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsalekinsirajus%2Friscvassembler","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsalekinsirajus%2Friscvassembler/lists"}