{"id":20549316,"url":"https://github.com/samiyaalizaidi/equalizer","last_synced_at":"2025-06-25T16:04:08.497Z","repository":{"id":241269536,"uuid":"802440057","full_name":"samiyaalizaidi/Equalizer","owner":"samiyaalizaidi","description":"Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications","archived":false,"fork":false,"pushed_at":"2024-12-28T16:26:35.000Z","size":549,"stargazers_count":5,"open_issues_count":1,"forks_count":1,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-01-16T16:41:32.639Z","etag":null,"topics":["audio-equalizer","audio-processing","digital-signal-processing","digital-signal-processing-filters","digital-system-design","digital-systems-design","equalizer","filter-design","fir-filters","fpga","verilog","verilog-hdl","xilinx-vivado"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/samiyaalizaidi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-05-18T09:53:11.000Z","updated_at":"2025-01-16T11:43:04.000Z","dependencies_parsed_at":null,"dependency_job_id":"b0cf6f92-60cc-4520-8865-d44795d8e727","html_url":"https://github.com/samiyaalizaidi/Equalizer","commit_stats":null,"previous_names":["samiyaalizaidi/equalizer"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/samiyaalizaidi%2FEqualizer","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/samiyaalizaidi%2FEqualizer/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/samiyaalizaidi%2FEqualizer/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/samiyaalizaidi%2FEqualizer/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/samiyaalizaidi","download_url":"https://codeload.github.com/samiyaalizaidi/Equalizer/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":242153392,"owners_count":20080493,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["audio-equalizer","audio-processing","digital-signal-processing","digital-signal-processing-filters","digital-system-design","digital-systems-design","equalizer","filter-design","fir-filters","fpga","verilog","verilog-hdl","xilinx-vivado"],"created_at":"2024-11-16T02:17:18.677Z","updated_at":"2025-03-06T05:28:22.956Z","avatar_url":"https://github.com/samiyaalizaidi.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Audio Equalizer Using FIR Filters\n\nThis project focuses on implementing a 32-tap low-pass Finite Impulse Response (FIR) filter for audio applications. Using a fixed-point representation, the filter is designed to allow frequencies below 500Hz while attenuating those above 1KHz. Verilog code is developed to create the filter's hardware architecture, and audio files are stored in ROM to test the filter's functionality. The project demonstrates effective low-pass filtering by passing a 100Hz tone while suppressing an 8KHz tone, validating its use in audio processing.\n\n\u003cp alight=\"center\"\u003e\n  \u003cimg src=\"img/process.png\" alt=\"process\"\u003e\n\u003c/p\u003e\n\n## Filter Coefficients\n\n### Filter Design\n\nFor this project, we extracted the filters using the ``MATLAB filterDesigner``. The following parameters were used to create the required filter:\n- Least-Squares Filter\n- Sampling Frequency, Fs: 40kHz\n- Transition Band: 500-1000Hz\n- Order: 31\n- Wpass: 1\n- Wstop: 1\n  \nAs a result, this was the magnitude response of the designed filter:\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"img/filter.PNG\" alt=\"Filter\"\u003e\n\u003c/p\u003e\n\n### Conversion to Binary\nTo represent the coefficients in signed 10-bit binary numbers, we scaled the coefficients by ``512`` and then converted the resulting fixed-point number into signed binary. These numbers were then used as parameters for the ``fir_low_pass_filter`` module in ``filter.v``. A ``MATLAB`` script was used for this process.\n\n## Input Audio\n\n### Generated Tones\n\nTwo audio tones were used to test the designed filter: one low-frequency audio of 100Hz, and the other high-frequency tone of 8kHz. The plots of the audio tones are shown below:\n\n\u003cp align=\"center\"\u003e\n  \u003cimg alt=\"100Hz\" src=\"img/100_original.png\"\u003e\n\u003c/p\u003e\n\n\u003cp align=\"center\"\u003e\n  \u003cimg alt=\"8kHz\" src=\"img/8000_original.png\"\u003e\n\u003c/p\u003e\n\n### Conversion to Binary\nTo convert the audio signals into 8-bit signed binary numbers, we first scaled the audio signal coefficients by a factor of ``128`` and then converted the fixed point numbers into signed binary numbers. These numbers were stored in a ``.txt`` file, and then eventually into a ``ROM`` module. For this process, a ``MATLAB`` script was used.\n\n## Verilog Implementation\n\nThere were three modules involved in the ``Verilog`` Implementation of this project: ROM, FIR Filter, and the Top-level Module.\n\n### ROM\n\nThe ROM module stores the values of the audio signal for both signals used in this case (in ``ROM_100Hz.v`` and ``ROM_8000Hz.v``). This module takes as input the address of the value that needs to be returned and returns the value associated with it on the positive edge of the clock.\n\n### FIR Filter\n\nThe module (in ``filter.v``) has the coefficients of the filter as signed parameters and takes the audio data as input. The audio data is first scaled down by a factor of 8, and then the convolution operation is performed. Shift registers are used to introduce the delays in the input signals.\n\n### Top-Level Module\nThe top-level module (in ``top_module.v``) simply connects the previous two modules, by passing the output of the ROM as the input into the FIR Filter.\n\n## Simulation\n\nThe testbench used for this module (in ``testbench.v``) instantiates the top-level module. There's also a ``repeat`` command used to increment the address of the value to be obtained from the ROM.\n\nThe waveform obtained when the ``100Hz`` signal was passed through the filter:\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"img/100hz.png\" alt=\"wf 100hz\"\u003e\n\u003c/p\u003e\n\nThe waveform obtained when the ``8kHz`` signal was passed through the filter:\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"img/8khz.png\" alt=\"wf 8khz\"\u003e\n\u003c/p\u003e\n\n---\n\n### Contributors\n- [Samiya Ali Zaidi](https://github.com/samiyaalizaidi)\n- [Huzaifah Tariq Ahmed](https://github.com/huzaifahtariqahmed)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsamiyaalizaidi%2Fequalizer","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsamiyaalizaidi%2Fequalizer","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsamiyaalizaidi%2Fequalizer/lists"}