{"id":19731427,"url":"https://github.com/sathyasris27/vlsi_design","last_synced_at":"2026-03-19T11:21:26.725Z","repository":{"id":218966518,"uuid":"353787421","full_name":"SathyasriS27/VLSI_Design","owner":"SathyasriS27","description":"Repository containing the simulated schematics of logic gates, counters, adders and registers along with corresponding layouts for semiconductor design.","archived":false,"fork":false,"pushed_at":"2021-09-01T17:58:13.000Z","size":73,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-01-10T17:53:41.459Z","etag":null,"topics":["boolean-logic","circuits","counters","semiconductors","vlsi-design"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/SathyasriS27.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2021-04-01T18:11:43.000Z","updated_at":"2024-06-11T17:59:04.000Z","dependencies_parsed_at":"2024-01-24T19:09:27.024Z","dependency_job_id":"a1394246-b1ca-47fb-b4a3-e7ffba7a5cd4","html_url":"https://github.com/SathyasriS27/VLSI_Design","commit_stats":null,"previous_names":["sathyasris27/vlsi_design"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SathyasriS27%2FVLSI_Design","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SathyasriS27%2FVLSI_Design/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SathyasriS27%2FVLSI_Design/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SathyasriS27%2FVLSI_Design/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/SathyasriS27","download_url":"https://codeload.github.com/SathyasriS27/VLSI_Design/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241056392,"owners_count":19901771,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["boolean-logic","circuits","counters","semiconductors","vlsi-design"],"created_at":"2024-11-12T00:20:56.876Z","updated_at":"2026-03-03T07:36:51.117Z","avatar_url":"https://github.com/SathyasriS27.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# **VLSI Design**\nRepository containing the simulated schematics of logic gates, counters, adders and registers along with corresponding layouts for semiconductor design.\n\nAll files have been compiled and tested using `DSCH2.exe` (for schematics) and `Microwind2.exe` (for semiconductor layout design).\n\n## **Designed Schematics and Layouts:**\n\n1. AND, OR and NOT Gates (Inverter)\n2. Function Design with XOR and XNOR\n3. Half, Full and Ripple-Carry Adders\n4. D Flip-Flop and Latch\n5. JK Flip-Flop and Latch\n6. Dynamic and Domino Logic for AND and OR Gates\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsathyasris27%2Fvlsi_design","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsathyasris27%2Fvlsi_design","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsathyasris27%2Fvlsi_design/lists"}