{"id":13649158,"url":"https://github.com/schoeberl/chisel-examples","last_synced_at":"2025-06-13T07:06:13.750Z","repository":{"id":8299261,"uuid":"14950867","full_name":"schoeberl/chisel-examples","owner":"schoeberl","description":"Chisel examples and code snippets","archived":false,"fork":false,"pushed_at":"2022-08-01T13:27:20.000Z","size":1160,"stargazers_count":246,"open_issues_count":1,"forks_count":78,"subscribers_count":20,"default_branch":"master","last_synced_at":"2025-03-05T12:47:54.775Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-2-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/schoeberl.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2013-12-05T10:43:09.000Z","updated_at":"2025-03-05T01:04:23.000Z","dependencies_parsed_at":"2022-07-13T13:50:53.425Z","dependency_job_id":null,"html_url":"https://github.com/schoeberl/chisel-examples","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/schoeberl/chisel-examples","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/schoeberl%2Fchisel-examples","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/schoeberl%2Fchisel-examples/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/schoeberl%2Fchisel-examples/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/schoeberl%2Fchisel-examples/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/schoeberl","download_url":"https://codeload.github.com/schoeberl/chisel-examples/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/schoeberl%2Fchisel-examples/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":259599328,"owners_count":22882356,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:48.777Z","updated_at":"2025-06-13T07:06:13.724Z","avatar_url":"https://github.com/schoeberl.png","language":"Tcl","readme":"# Chisel Examples\n\nThis repository is a collection of code examples for [Chisel](https://chisel.eecs.berkeley.edu/).\n\nThis collection has been moved to the latest version of Chisel, Chisel 3.\nI have collected notes on this move in [TowardsChisel3](TowardsChisel3.md)\n\n# Getting the Examples\n\n    $ git clone https://github.com/schoeberl/chisel-examples.git\n\nThe collection is organized as follows:\n\n**hello-world** is a self contained minimal project for a blinking LED in an FPGA.\n\nThe rest of the examples are rooted in the current folder.\n\n# Needed Tools\n\n * A recent version of Java (JDK 8 or later)\n\n * The Scala build tool [sbt](http://www.scala-sbt.org/)\n\n\n# Running the examples\n\nmake alu\n\tGenerates the Verilog files for the small ALU.\n\tSynthesize it for the DE0 board with Quartus and the alu project file.\n\nmake alu-test\n\tGenerats the C++ based simulation and runs the tests.\n\nSee the Makefile for further examples, or simply run `sbt run` to see all objects with a main.\n\n## Notes using the DE10-Nano\n\nChange switches for FPGA configuration to:\n\n```\n+------+\n|* ** *|\n| *  * |\n+------+\n```\n\nProbably add USB blaster permissions for: Bus 001 Device 005: ID 09fb:6810 Altera and 09fb:6010\n\nA TTL UART is connected to GPIO pins 1 and 2 of GPIO 0.\n\n```\nGND * *\n    * *\n    * *\n    * *\n    * *\ntxd * * rxd (pin 1)\n```\n\nrxd and txd are from the FPGA view, therefore TTL UART rxd needs to\nbe connected to txd (pin 2) and the other way around.\n","funding_links":[],"categories":["Tcl"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fschoeberl%2Fchisel-examples","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fschoeberl%2Fchisel-examples","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fschoeberl%2Fchisel-examples/lists"}