{"id":43288079,"url":"https://github.com/secworks/prince","last_synced_at":"2026-02-01T18:04:25.711Z","repository":{"id":56273324,"uuid":"201984065","full_name":"secworks/prince","owner":"secworks","description":"The Prince lightweight block cipher in Verilog.","archived":false,"fork":false,"pushed_at":"2026-01-17T10:44:37.000Z","size":120,"stargazers_count":12,"open_issues_count":0,"forks_count":7,"subscribers_count":2,"default_branch":"master","last_synced_at":"2026-01-17T22:08:33.322Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-2-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/secworks.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-08-12T18:09:57.000Z","updated_at":"2026-01-17T10:44:41.000Z","dependencies_parsed_at":"2025-03-30T18:19:29.232Z","dependency_job_id":"a68db7fc-fd8c-4d1b-b315-2d7f53d8a33b","html_url":"https://github.com/secworks/prince","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/secworks/prince","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fprince","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fprince/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fprince/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fprince/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/secworks","download_url":"https://codeload.github.com/secworks/prince/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fprince/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28984859,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-01T17:52:09.146Z","status":"ssl_error","status_checked_at":"2026-02-01T17:49:53.529Z","response_time":56,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2026-02-01T18:04:25.050Z","updated_at":"2026-02-01T18:04:25.706Z","avatar_url":"https://github.com/secworks.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# prince\nThe Prince lightweight block cipher in Verilog.\n\n## Status\nCore is functionally completed. Both core and top level provides correct\nresults for all test vectors. The core is lint clean. The core has been\nimplemented in hardware.\n\n\n## Introduction\n[Prince](https://eprint.iacr.org/2012/529.pdf) is a lightweight, low\nlatency block cipher suitable for Iot and embedded systems. The key is\n128 bits and the block size is 64 bits.\n\n### Contact information ##\n\nAssured provides customer support including customization, integration\nand system development related to the core. For more information,\nplease contact [Assured Security\nConsultants](https://www.assured.se/contact).\n\n\n## Implementation details\nThe implementation is currently a pipelined designs with three pipeline\nstages. With a cycle to initalize the state and a cycle for latching the\nresult the latency is five cycles. The design does not use any RAM\nblocks nor DSPs.\n\n\n## FuseSoC\nThis core is supported by the\n[FuseSoC](https://github.com/olofk/fusesoc) core package manager and\nbuild system. Some quick  FuseSoC instructions:\n\nInstall FuseSoC\n~~~\npip install fusesoc\n~~~\n\nCreate and enter a new workspace\n~~~\nmkdir workspace \u0026\u0026 cd workspace\n~~~\n\nRegister prince as a library in the workspace\n~~~\nfusesoc library add prince /path/to/prince\n~~~\n...if repo is available locally or...\n...to get the upstream repo\n~~~\nfusesoc library add prince https://github.com/secworks/prince\n~~~\n\nRun tb_prince testbench\n~~~\nfusesoc run --target=tb_prince secworks:crypto:prince\n~~~\n\nRun with modelsim instead of default tool (icarus)\n~~~\nfusesoc run --target=tb_prince --tool=modelsim secworks:crypto:prince\n~~~\n\n\n## Implementation results\n\n### Altera Cyclone V\n* Device: 5CGXFC7C7F23C8\n* Tool version: Intel Quartus Prime 19.1\n* ALMs: 993\n* Regs: 716\n* Fmax: 102 MHz\n\n### Xilinx Artix-7\n* Device: xc7a200tsbv484-2\n* Tool version: Vivado 2019.2\n* LUTs: 1587\n* FFs: 646\n* Fmax: 150 MHz\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsecworks%2Fprince","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsecworks%2Fprince","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsecworks%2Fprince/lists"}