{"id":43288135,"url":"https://github.com/secworks/sha1","last_synced_at":"2026-02-01T18:04:33.052Z","repository":{"id":13662100,"uuid":"16355710","full_name":"secworks/sha1","owner":"secworks","description":"Verilog implementation of the SHA-1 cryptgraphic hash function","archived":false,"fork":false,"pushed_at":"2025-04-03T08:38:22.000Z","size":489,"stargazers_count":52,"open_issues_count":0,"forks_count":18,"subscribers_count":7,"default_branch":"master","last_synced_at":"2025-04-03T09:32:47.751Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-2-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/secworks.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2014-01-29T19:25:22.000Z","updated_at":"2025-04-03T08:38:27.000Z","dependencies_parsed_at":"2022-09-10T14:40:41.875Z","dependency_job_id":null,"html_url":"https://github.com/secworks/sha1","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/secworks/sha1","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha1","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha1/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha1/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha1/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/secworks","download_url":"https://codeload.github.com/secworks/sha1/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha1/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28984867,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-01T17:52:09.146Z","status":"ssl_error","status_checked_at":"2026-02-01T17:49:53.529Z","response_time":56,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2026-02-01T18:04:32.980Z","updated_at":"2026-02-01T18:04:33.047Z","avatar_url":"https://github.com/secworks.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"sha1\n====\nVerilog implementation of the SHA-1 cryptgraphic hash function.\n\n## Implementation status ##\nThe core has been completed and been used in several designs. It is\nconsidered mature and ready to use.. Minor changes are non-functional\ncleanups of code.\n\n\n## Introduction ##\nVerilog implementation of the SHA-1 cryptgraphic hash function. The\nfunctionality follows the specification in NIST FIPS 180-4.\n\nThe implementation is iterative with one cycle/round. The initialization\ntakes one cycle. The W memory is based around a sliding window of 16\n32-bit registers that are updated in sync with the round processing. The\ntotal latency/message block is 82 cycles.\n\nThere are top level wrappers that provides interface for easy\nintegration into a System on Chip (SoC). This interface contains mesage\nblock and digest registers to allow a host to load the next block while\nthe current block is being processed.\n\nThe implementation also includes a functional model written in Python.\n\n\n### Contact information ##\nAssured provides customer support including customization, integration\nand system development related to the core. For more information,\nplease contact [Assured Security\nConsultants](https://www.assured.se/contact).\n\n\n## Implementation details ##\n\nThe sha1 design is divided into the following sections.\n- src/rtl - RTL source files\n- src/tb  - Testbenches for the RTL files\n- src/model/python - Functional model written in python\n- doc - documentation (currently not done.)\n- toolruns - Where tools are supposed to be run. Includes a Makefile for\nbuilding and simulating the design using [Icarus Verilog](http://iverilog.icarus.com/)\n\nThe actual core consists of the following files:\n- sha1_core.v - The core itself with wide interfaces.\n- sha1_w_mem.v - W message block memort and expansion logic.\n\nThe top level entity is called sha1_core. This entity has wide\ninterfaces (512 bit block input, 160 bit digest). In order to make it\nusable you probably want to wrap the core with a bus interface.\n\nUnless you want to provide your own interface you therefore also need to\nuse a top level wrapper. There is one wrapper provided:\n- sha1.v - A wrapper with a 32-bit memory like interface.\n\nThe core (sha1_core) will sample all data inputs when given the init\nor next signal. the wrappers provided contains additional data\nregisters. This allows you to load a new block while the core is\nprocessing the previous block.\n\n\n## FuseSoC\nThis core is supported by the\n[FuseSoC](https://github.com/olofk/fusesoc) core package manager and\nbuild system. Some quick  FuseSoC instructions:\n\nInstall FuseSoC\n~~~\npip install fusesoc\n~~~\n\nCreate and enter a new workspace\n~~~\nmkdir workspace \u0026\u0026 cd workspace\n~~~\n\nRegister sha1 as a library in the workspace\n~~~\nfusesoc library add sha1 /path/to/sha1\n~~~\n...if repo is available locally or...\n...to get the upstream repo\n~~~\nfusesoc library add sha1 https://github.com/secworks/sha1\n~~~\n\nRun tb_sha1 testbench\n~~~\nfusesoc run --target=tb_sha1 secworks:crypto:sha1\n~~~\n\nRun with modelsim instead of default tool (icarus)\n~~~\nfusesoc run --target=tb_sha1 --tool=modelsim secworks:crypto:sha1\n~~~\n\n## FPGA-results ##\n\n### Altera Cyclone FPGAs ###\nImplementation results using Altera Quartus-II 13.1.\n\n**Altera Cyclone IV E**\n- EP4CE6F17C6\n- 2913 LEs\n- 1527 regs\n- 107 MHz\n\n**Altera Cyclone IV GX**\n- EP4CGX22CF19C6\n- 2814 LEs\n- 1527 regs\n- 105 MHz\n\n**Altera Cyclone V**\n- 5CGXFC7C7F23C8\n- 1124 ALMs\n- 1527 regs\n- 104 MHz\n\n\n### Xilinx FPGAs ###\nImplementation results using ISE 14.7.\n\n**Xilinx Spartan-6**\n- xc6slx45-3csg324\n- 1589 LUTs\n- 564 Slices\n- 1592 regs\n- 100 MHz\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsecworks%2Fsha1","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsecworks%2Fsha1","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsecworks%2Fsha1/lists"}