{"id":13649332,"url":"https://github.com/secworks/sha256","last_synced_at":"2026-01-11T00:55:06.893Z","repository":{"id":12689481,"uuid":"15361741","full_name":"secworks/sha256","owner":"secworks","description":"Hardware implementation of the SHA-256 cryptographic hash function","archived":false,"fork":false,"pushed_at":"2025-04-03T08:44:34.000Z","size":379,"stargazers_count":334,"open_issues_count":0,"forks_count":97,"subscribers_count":26,"default_branch":"master","last_synced_at":"2025-04-03T09:33:29.303Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-2-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/secworks.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2013-12-21T16:18:17.000Z","updated_at":"2025-04-03T08:44:38.000Z","dependencies_parsed_at":"2024-01-07T01:18:25.603Z","dependency_job_id":"cb1e33f0-9f9c-497f-9a8f-9b1312029d84","html_url":"https://github.com/secworks/sha256","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha256","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha256/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha256/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha256/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/secworks","download_url":"https://codeload.github.com/secworks/sha256/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258949,"owners_count":21401003,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:57.205Z","updated_at":"2025-04-22T14:31:20.683Z","avatar_url":"https://github.com/secworks.png","language":"Verilog","funding_links":[],"categories":["Verilog","Accelerators"],"sub_categories":[],"readme":"[![build-openlane-sky130](https://github.com/secworks/sha256/actions/workflows/ci.yml/badge.svg?branch=master\u0026event=push)](https://github.com/secworks/sha256/actions/workflows/ci.yml)\n\n# sha256 #\n\n## Implementation status ##\nThe core has been completed for a long time and been used in several\ndesigns in ASICs as well as in FPGAs. The core is considered mature and\nready for use. Minor changes are non-functional cleanups of code.\n\n\n## Introduction\nHardware implementation of the SHA-256 cryptographic hash function with\nsupport for both SHA-256 and SHA-224. The implementation is written in\nVerilog 2001 compliant code. The implementation includes the main core\nas well as wrappers that provides interfaces for simple integration.\n\nThis is a low area implementation that iterates over the rounds but\nthere is no sharing of operations such as adders.\n\nThe hardware implementation is complemented by a functional model\nwritten in Python.\n\nNote that the core does **NOT** implement padding of final block. The\ncaller is expected to handle padding.\n\n\n## Implementation details ##\nThe sha256 design is divided into the following sections.\n- src/rtl - RTL source files\n- src/tb  - Testbenches for the RTL files\n- src/model/python - Functional model written in python\n- doc - documentation (currently not done.)\n- toolruns - Where tools are supposed to be run. Includes a Makefile for\nbuilding and simulating the design using\n[Icarus Verilog](http://iverilog.icarus.com/). There are also targets\nfor linting the core using [Verilator](http://www.veripool.org/wiki/verilator).\n\nThe actual core consists of the following files:\n- sha256_core.v - The core itself with wide interfaces.\n- sha256_w_mem.v - W message block memory and block expansion logic.\n- sha256_k_constants.v - K constants ROM memory.\n\nThe top level entity is called sha256_core. This entity has wide\ninterfaces (512 bit block input, 256 bit digest). In order to make it\nusable you probably want to wrap the core with a bus interface.\n\n\nThe provided top level wrapper, sha256.v provides a simple 32-bit memory\nlike interface. The core (sha256_core) will sample all data inputs when\ngiven the init or next signal. the wrapper contains additional data\nregisters. This allows you to load a new block while the core is\nprocessing the previous block.\n\n\nThe core supports both sha224 and sha256 modes. The default mode is\nsha256. The mode bit is located in the ADDR_CTRL API register and this\nmeans that when writing to this register to start processing a block,\ncare must be taken to set the mode bit to the intended mode. This means\nthat old code that for example simply wrote 0x01 to initiate SHA256\nprocessing will now initiate SHA224 processing. Writing 0x05 will\nnow initiate SHA256 processing.\n\nRegarding SHA224, it is up to the user to only read seven, not eight\nwords from the digest registers. The core will update the LSW too.\n\n\n## Streaming interface ##\nThere is a streaming interface for the core contributed by\n[Olof Kindgren](https://github.com/olofk).\n\n- src/interfaces/stream/rtl - RTL source file for wrapped core\n- src/interfaces/stream/tb - Testbench for the wrapped core\n\n\n## AXI4 interface ##\n\n**NOTE** This interface is currently being developed. Expect bugs as this\ninterface is still under development.\n\nThere is now an AXI4 interface for the core contributed by\n[Sanjay A Menon](https://github.com/Sanjay-A-Menon). The interface wraps\nsha256_core, replacing sha256.v\n\nThe interface provides an AXI4-Lite slave interface with added hash\ncomplete interrupt signal. Chip select is implemented via axi_awprot\nsignal.\n\n- src/interfaces/axi4/rtl - RTL source file for wrapped core\n- src/interfaces/axi4/tb  - Testbench for the wrapped core\n\n\n\n## FuseSoC Integration\nThis core is supported by the\n[FuseSoC](https://github.com/olofk/fusesoc) core package manager and\nbuild system. Some quick  FuseSoC instructions:\n\ninstall FuseSoC\n~~~\npip install fusesoc\n~~~\n\nCreate and enter a new workspace\n~~~\nmkdir workspace \u0026\u0026 cd workspace\n~~~\n\nRegister sha256 as a library in the workspace\n~~~\nfusesoc library add sha256 /path/to/sha256\n~~~\n\n...if repo is available locally or...\n...to get the upstream repo\n~~~\nfusesoc library add sha256 https://github.com/secworks/sha256\n~~~\n\nTo run lint\n~~~\nfusesoc run --target=lint secworks:crypto:sha256\n~~~\n\nRun tb_sha256 testbench\n~~~\nfusesoc run --target=tb_sha256 secworks:crypto:sha256\n~~~\n\nRun with modelsim instead of default tool (icarus)\n~~~\nfusesoc run --target=tb_sha256 --tool=modelsim secworks:crypto:sha256\n~~~\n\nList all targets\n~~~\nfusesoc core show secworks:crypto:sha256\n~~~\n\n\n## ASIC-results ##\nImplementation in 40 nm low power standard cell process.\n- Area: 14200 um2\n- Combinational cells: 2344.9230\n- Non-combinational cells: 2902.4856\n- Clock frequency: 250 MHz\n\n\n## Fpga-results ##\n\n### Altera Cyclone FPGAs ###\nImplementation results using Altera Quartus-II 13.1.\n\n**Cyclone IV E**\n- EP4CE6F17C6\n- 3882 LEs\n- 1813 registers\n- 74 MHz\n- 66 cycles latency\n\n**Cyclone IV GX**\n- EP4CGX22CF19C6\n- 3773 LEs\n- 1813 registers\n- 76 MHz\n- 66 cycles latency\n\n**Cyclone V**\n- 5CGXFC7C7F23C8\n- 1469 ALMs\n- 1813 registers\n- 79 MHz\n- 66 cycles latency\n\n\n### Microchip ###\n\n***IGLOO2***\n- Tool: Libero v 12.4\n- Device: M2GL090TS-1FG484I\n- LUTs: 2811\n- SLEs: 1900\n- BRAMs: 0\n- Fmax: 114 MHz\n\n\n### Xilinx FPGAs ###\nImplementation results using ISE 14.7.\n\n**Spartan-6**\n- xc6slx45-3csg324\n- 2012 LUTs\n- 688 Slices\n- 1929 regs\n- 70 MHz\n- 66 cycles latency\n\n**Artix-7**\n- xc7a200t-3fbg484\n- 2471 LUTs\n- 747 Slices\n- 1930 regs\n- 108 MHz\n- 66 cycles latency\n\n\nImplementation results using Vivado 2014.4.\n\n**Zynq-7030**\n- xc7z030fbg676-1\n- 2308 LUTs\n- 796 Slices\n- 2116 regs\n- 116 MHz\n- 66 cycles latency\n\n\nImplementation results using Vivado v.2019.2\n\nResults kindly provided by\n[Sanjay-A-Menon](https://github.com/Sanjay-A-Menon). Implemented design\nincludes the AXI4 wrapper.\n\n**Zynq-7020**\n- Device: 7z020clg400-1\n- Slice LUTs: 2555\n- Slice regs: 2606\n- Fmax: 78 MHz\n- 66 cycles latency\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsecworks%2Fsha256","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsecworks%2Fsha256","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsecworks%2Fsha256/lists"}