{"id":13649376,"url":"https://github.com/secworks/sha512","last_synced_at":"2026-02-01T18:04:25.633Z","repository":{"id":14406226,"uuid":"17116976","full_name":"secworks/sha512","owner":"secworks","description":"Verilog implementation of the SHA-512 hash function.","archived":false,"fork":false,"pushed_at":"2026-01-17T10:42:53.000Z","size":161,"stargazers_count":44,"open_issues_count":1,"forks_count":21,"subscribers_count":5,"default_branch":"master","last_synced_at":"2026-01-17T22:07:53.609Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-2-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/secworks.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2014-02-23T21:00:01.000Z","updated_at":"2026-01-17T10:42:57.000Z","dependencies_parsed_at":"2025-04-22T14:40:31.424Z","dependency_job_id":"430883a2-47dd-4ce6-9c29-91ccdfb44a4d","html_url":"https://github.com/secworks/sha512","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/secworks/sha512","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha512","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha512/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha512/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha512/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/secworks","download_url":"https://codeload.github.com/secworks/sha512/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/secworks%2Fsha512/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28984859,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-01T17:52:09.146Z","status":"ssl_error","status_checked_at":"2026-02-01T17:49:53.529Z","response_time":56,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:58.518Z","updated_at":"2026-02-01T18:04:25.628Z","avatar_url":"https://github.com/secworks.png","language":"Verilog","funding_links":[],"categories":["Verilog","Accelerators"],"sub_categories":[],"readme":"sha512\n======\n## Status ##\nThe core is completed and is considered mature. The core has been used\nin more than one FPGA design.\n\n## Introduction\nVerilog implementation of the SHA-512 hash function. This implementation\ncomplies with the functionality in NIST FIPS 180-4. The implementation\nsupports the SHA-512 variants SHA-512/224, SHA-512/256, SHA-384 and\nSHA-512.\n\n### Contact information ##\n\nAssured provides customer support including customization, integration\nand system development related to the core. For more information,\nplease contact [Assured Security\nConsultants](https://www.assured.se/contact).\n\n\n## Implementation details ##\nThe core uses a sliding window with 16 64-bit registers for the W\nmemory. The top level wrapper contains flag control registers for init\nand next that automatically resets. This means that the flags must be\nset for every block to be processed.\n\n## FuseSoC\nThis core is supported by the\n[FuseSoC](https://github.com/olofk/fusesoc) core package manager and\nbuild system. Some quick  FuseSoC instructions:\n\nInstall FuseSoC\n~~~\npip install fusesoc\n~~~\n\nCreate and enter a new workspace\n~~~\nmkdir workspace \u0026\u0026 cd workspace\n~~~\n\nRegister sha512 as a library in the workspace\n~~~\nfusesoc library add sha512 /path/to/sha512\n~~~\n...if repo is available locally or...\n...to get the upstream repo\n~~~\nfusesoc library add sha512 https://github.com/secworks/sha512\n~~~\n\nRun tb_sha512 testbench\n~~~\nfusesoc run --target=tb_sha512 secworks:crypto:sha512\n~~~\n\nRun with modelsim instead of default tool (icarus)\n~~~\nfusesoc run --target=tb_sha512 --tool=modelsim secworks:crypto:sha512\n~~~\n\n## Implementation results\n\n### Xilinx FPGAs ###\nImplementation results using ISE 14.7.\n\n***Artix-7***\n- xc7a200t-3fbg484\n- 4869 Slice LUTs\n- 1575 Slices\n- 3918 regs\n- 96 MHz\n\n\n***Spartan-6***\n- xc6slx45-3csg324\n- 4333 LUTs\n- 1300 Slices\n- 3853 regs\n- 57 MHz\n\n\n### Altera FPGAs ###\n\n***Altera Cyclone V GX***\n- 2923 ALMs\n- 3609 Registers\n- 80 MHz max clock frequency\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsecworks%2Fsha512","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsecworks%2Fsha512","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsecworks%2Fsha512/lists"}