{"id":13996057,"url":"https://github.com/seldridge/verilog","last_synced_at":"2026-01-28T04:34:49.434Z","repository":{"id":2791334,"uuid":"3791379","full_name":"seldridge/verilog","owner":"seldridge","description":"Repository for basic (and not so basic) Verilog blocks with high re-use potential","archived":false,"fork":false,"pushed_at":"2018-03-15T15:01:03.000Z","size":74,"stargazers_count":564,"open_issues_count":0,"forks_count":140,"subscribers_count":52,"default_branch":"master","last_synced_at":"2025-03-28T00:41:07.374Z","etag":null,"topics":["fpga","hardware","rtl","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/seldridge.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2012-03-21T21:06:25.000Z","updated_at":"2025-03-26T10:18:27.000Z","dependencies_parsed_at":"2022-07-16T23:06:58.505Z","dependency_job_id":null,"html_url":"https://github.com/seldridge/verilog","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/seldridge/verilog","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/seldridge%2Fverilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/seldridge%2Fverilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/seldridge%2Fverilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/seldridge%2Fverilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/seldridge","download_url":"https://codeload.github.com/seldridge/verilog/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/seldridge%2Fverilog/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28838487,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-28T02:10:51.810Z","status":"ssl_error","status_checked_at":"2026-01-28T02:10:50.806Z","response_time":57,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","hardware","rtl","verilog"],"created_at":"2024-08-09T14:03:47.364Z","updated_at":"2026-01-28T04:34:49.420Z","avatar_url":"https://github.com/seldridge.png","language":"Verilog","funding_links":[],"categories":["Verilog"],"sub_categories":[],"readme":"## Description\n\nRepository for Verilog building blocks with a high chance of reuse\nacross different hardware projects (e.g. debouncers, display drivers).\n\nMost of these modules are well tested and shouldn't have issues.\nHowever, I'm generally allowing myself to upload things which *may*\nhave issues.\n\n## Modules\n\n* `button_debounce.v` -- Timing-based button debouncing circuit.\n\n* `pipeline_registers.v` -- A parameterized number of pipeline\n  registers of some depth and width. This is primarily useful as a\n  building block for _other_ modules.\n\n* `pipeline_registers_set.v` -- Pipeline registers (as above), but\n  with the ability to _set_ the value of the registers.\n\n* `ram_infer.v` -- Xilinx standard module that will infer RAM during\n  FPGA synthesis.\n\n* `reset.v` -- Implements a \"good\" reset with asynchronous assertion\n  and synchronous de-assertion.\n\n* `sign_extender.v` -- Explicit sign extender (this should be\n  unnecessary in Verilog...)\n\n* `sqrt_pipelined.v` -- A pipelined implementation of a fixed point\n  square root. **Deprecated due to complexity and incorrect rounding**.\n\n* `sqrt_generic.v` -- A refactor of `sqrt_pipelined.v` into a cleaner\n  syntax. This uses implicit truncation rounding and will show a\n  resulting bias towards negative infinity.\n\n* `uart_rx.v` -- UART receiver.\n\n* `uart_tx.v` -- UART transmitter.\n\n* `div_pipelined.v` -- Pipelined division module (**largely untested**)\n\n## Submodules\n\nIn an attempt at modularity, I'm now including a submodules directory\nwhich is intended to contain other repositories (of mine most likely,\nbut not restricted as such) that are useful. These can be pulled in\nwith:\n\n```\ngit submodule init\ngit submodule update\n```\n\nAnd recursively updated with:\n\n```\ngit submodule foreach git pull origin master\n```\n\n* [hdl-tools](https://github.com/ibm/hdl-tools) --\n  Basically, a dumping ground of scripts I've written that make\n  working with HDLs easier. For example, `addWavesRecursive.tcl` will\n  populate a GTKWave configuration with the module hierarchy found in\n  a VCD file.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fseldridge%2Fverilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fseldridge%2Fverilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fseldridge%2Fverilog/lists"}