{"id":28220430,"url":"https://github.com/septemus/swjtu_computer_organization_exp3_multiply","last_synced_at":"2026-02-08T18:01:27.996Z","repository":{"id":161355952,"uuid":"630260990","full_name":"Septemus/swjtu_computer_organization_exp3_multiply","owner":"Septemus","description":"西南交通大学计组实验3-原码1位乘法运算器设计","archived":false,"fork":false,"pushed_at":"2024-04-09T05:50:37.000Z","size":6942,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-06-11T15:39:14.107Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Septemus.png","metadata":{"files":{"readme":"readme.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2023-04-20T02:22:11.000Z","updated_at":"2025-04-21T01:12:56.000Z","dependencies_parsed_at":null,"dependency_job_id":"430c1a41-1513-4df5-843d-99fb5192456a","html_url":"https://github.com/Septemus/swjtu_computer_organization_exp3_multiply","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Septemus/swjtu_computer_organization_exp3_multiply","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp3_multiply","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp3_multiply/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp3_multiply/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp3_multiply/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Septemus","download_url":"https://codeload.github.com/Septemus/swjtu_computer_organization_exp3_multiply/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp3_multiply/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":267417664,"owners_count":24083839,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-07-27T02:00:11.917Z","response_time":82,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-05-18T04:15:26.189Z","updated_at":"2026-02-08T18:01:22.953Z","avatar_url":"https://github.com/Septemus.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003e # 0 关于\n\n欢迎到我的博客文章查看更多内容😄：\n[https://septemus.github.io/computer_organization_exp3/\n](https://septemus.github.io/computer_organization_exp3/)\n\u003e # 1 实验内容\n\n用verilog设计一个8位原码一位乘法运算器。乘数和被乘数均为8位原码，被乘数存放在B寄存器中；C寄存器的初始值存放乘数，运算结束后存放乘积的低位部分；A寄存器用于存放部分积，其初始值是0，运算结束后存放乘积的高位部分。A寄存器和C寄存器可级联在一起右移，CR为乘法步数计数器，在每个时钟信号上升沿处理一位乘法的累加和右移，根据乘数的最低位是否为1决定是加被乘数还是0，乘积的符号位由被乘数和乘数的符号位异或得到\n\n\u003e # 2 代码/原理图\n\n\u003e ## 2.1 顶层文件\n\n```Verilog\n\n module exp3_2(\n    input clk,\n\t input [3:0] KEY_R,\n\t input clr,\n\t input flag1,\n\t input flag2,\n\t input en,\n\t output wire flag3,\n\t output [3:0] KEY_C = 4'b0111,\n\t output reg[15:0]ans,\n\t output reg[8:0] a,\n\t output reg[7:0] b,\n\t output reg[7:0] c,\n\t output reg[3:0] cr_reg,\n\t output wire[31:0] N,\n\t output [7:0] codeout,\n\t output [2:0] sel =3'b000\n);\nwire [7:0] X,Y;\nwire [15:0] key_out;\nkeymodule km(.clk(clk),.KEY_R(KEY_R),.clr(clr),.KEY_C(KEY_C),.out(key_out)\n);\nmidware (key_out,X,Y);\nassign flag3=flag1^flag2;\nassign N={X,Y,ans};\nsegment_displays sd(.clk(clk),.N(N),.seg(codeout),.sel(sel));\ninitial\nbegin\n\tcr_reg\u003c=4'b0000;\nend\nalways @(posedge clk) \nbegin\n\tif(en)\n\tbegin\n\t if(cr_reg==4'b0000)\n\t begin\n\t\ta\u003c=0;\n\t\tb\u003c=X[7:0];\n\t\tc\u003c=Y[7:0];\n\t\tcr_reg\u003c=4'b0001;\n\t end\n\t else\n\t begin\n\t\t\tif(cr_reg==4'b1001)\n\t\t\tbegin \n\t\t\t\tans\u003c={a[7:0],c};\n\t\t\t\tcr_reg\u003c=4'b0000;\n\t\t\tend\n\t\t\telse\n\t\t\tbegin\n\t\t\t\tif(c\u00261)\n\t\t\t\tbegin\n\t\t\t\t\ta=a+{1'b0,b};\n\t\t\t\tend\n\t\t\t\tc={a\u00261,c[7:1]};\n\t\t\t\ta=a\u003e\u003e1;\n\t\t\t\tcr_reg\u003c=cr_reg+1;\n\t\t\tend\n\t end\n\t end\nend\nendmodule\n\n```\n\n\u003e ## 2.2 根据键盘获取输入\n\n```Verilog\nmodule keymodule(\n\tinput clk,\n\tinput [3:0] KEY_R,\n\tinput clr,\n\toutput reg[3:0] KEY_C = 4'b0111,\n\toutput reg[15:0] out= 16'hxxxx\n);\n\treg [1:0] cnt = 2'b0;\n\treg[4:0] num=5'd16;\n\treg[31:0] count_num=32'b1;\n//根据按钮的列扫描信号和行输入信号判断按钮是否被按下\nalways  @(posedge clk,posedge clr)\nbegin\n\t\tif(clr)\n\t\tbegin\n\t\t\tcnt\u003c=2'b0;\n\t\t\tout\u003c=16'hxxxx;\n\t\tend\n\t\telse\n\t\tbegin\n\t\t\tcnt = cnt + 1'b1;\n\t\t\tcase (cnt)\n\t\t\t\t2'b00:\tKEY_C \u003c= 4'b1110;\n\t\t\t\t2'b01:\tKEY_C \u003c= 4'b1101;\n\t\t\t\t2'b10:\tKEY_C \u003c= 4'b1011;\n\t\t\t\t2'b11:\tKEY_C \u003c= 4'b0111;         \n\t\t\tendcase\n\t\t\tif(KEY_R==4'b1111)\n\t\t\tbegin\n\t\t\t\tnum=5'd16;\n\t\t\tend\n\t\t\telse \n\t\t\tbegin \n\t\t\t\t  case ({KEY_C, KEY_R})\n\t\t\t\t\t \n\t\t\t\t\t 8'b1011_1110: num = 5'd0;\n\t\t\t\t\t 8'b0111_0111: num = 5'd1;\n\t\t\t\t\t 8'b1011_0111: num = 5'd2;\n\t\t\t\t\t 8'b1101_0111: num = 5'd3;\n\t\t\t\t\t \n\t\t\t\t\t 8'b0111_1011: num = 5'd4;\n\t\t\t\t\t 8'b1011_1011: num = 5'd5;\n\t\t\t\t\t 8'b1101_1011: num = 5'd6;\n\t\t\t\t\t 8'b0111_1101: num = 5'd7;  \n\t\t\t\t\t \n\t\t\t\t\t 8'b1011_1101: num = 5'd8;\n\t\t\t\t\t 8'b1101_1101: num = 5'd9;\n\t\t\t\t\t 8'b1110_0111: num = 5'd10;\n\t\t\t\t\t 8'b1110_1011: num = 5'd11;  \n\t\t\t\t\t \n\t\t\t\t\t 8'b1110_1101: num = 5'd12;\n\t\t\t\t\t 8'b1110_1110: num = 5'd13;\n\t\t\t\t\t 8'b0111_1110: num = 5'd14;\n\t\t\t\t\t 8'b1101_1110: num = 5'd15;  \n\t\t\t\t  endcase\n\t\t\tend\n\t\t\tbegin\n\t\t\t\tif(num == 5'b1_0000)\n\t\t\t\t\tbegin\n\t\t\t\t\t\tif(count_num == 32'b0)begin\n\t\t\t\t\t\t\tcount_num = 32'd100001;end\n\t\t\t\t\t\tcount_num = count_num + 1'b1;\n\t\t\t\t\tend\n\t\t\t\telse if(count_num \u003e 32'd100000)\n\t\t\t\t\tbegin\n\t\t\t\t\t\tcount_num = 32'b1;\n\t\t\t\t\t\n\t\t\t\t\t\t//移位\n\t\t\t\t\t\tbegin\n\t\t\t\t\t\tout=out\u003c\u003c4;\n\t\t\t\t\t\tout[3:0] = num[3:0];\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\tend\n\t\t\tend\n\t\t\nend\nendmodule   \n```\n\n\u003e ### 2.2.1 仿真用key_module\n\n```Verilog\nmodule keymodule(\n\tinput clk,\n\tinput [3:0] KEY_R,\n\tinput clr,\n\toutput reg[3:0] KEY_C = 4'b0111,\n\toutput reg[15:0] out= 16'hxxxx\n);\n\treg [1:0] cnt = 2'b0;\n\treg[4:0] num=5'd16;\n\treg[31:0] count_num=32'b1;\n//根据按钮的列扫描信号和行输入信号判断按钮是否被按下\nalways  @(posedge clk,posedge clr)\nbegin\n\t\tif(clr)\n\t\tbegin\n\t\t\tcnt\u003c=2'b0;\n\t\t\tout\u003c=16'hxxxx;\n\t\tend\n\t\telse\n\t\tbegin\n\t\t\tcnt = cnt + 1'b1;\n\t\t\tcase (cnt)\n\t\t\t\t2'b00:\tKEY_C \u003c= 4'b1110;\n\t\t\t\t2'b01:\tKEY_C \u003c= 4'b1101;\n\t\t\t\t2'b10:\tKEY_C \u003c= 4'b1011;\n\t\t\t\t2'b11:\tKEY_C \u003c= 4'b0111;         \n\t\t\tendcase\n\t\t\tif(KEY_R==4'b1111)\n\t\t\tbegin\n\t\t\t\tnum=5'd16;\n\t\t\tend\n\t\t\telse \n\t\t\tbegin \n\t\t\t\t  case ({KEY_C, KEY_R})\n\t\t\t\t\t \n\t\t\t\t\t 8'b1011_1110: num = 5'd0;\n\t\t\t\t\t 8'b0111_0111: num = 5'd1;\n\t\t\t\t\t 8'b1011_0111: num = 5'd2;\n\t\t\t\t\t 8'b1101_0111: num = 5'd3;\n\t\t\t\t\t \n\t\t\t\t\t 8'b0111_1011: num = 5'd4;\n\t\t\t\t\t 8'b1011_1011: num = 5'd5;\n\t\t\t\t\t 8'b1101_1011: num = 5'd6;\n\t\t\t\t\t 8'b0111_1101: num = 5'd7;  \n\t\t\t\t\t \n\t\t\t\t\t 8'b1011_1101: num = 5'd8;\n\t\t\t\t\t 8'b1101_1101: num = 5'd9;\n\t\t\t\t\t 8'b1110_0111: num = 5'd10;\n\t\t\t\t\t 8'b1110_1011: num = 5'd11;  \n\t\t\t\t\t \n\t\t\t\t\t 8'b1110_1101: num = 5'd12;\n\t\t\t\t\t 8'b1110_1110: num = 5'd13;\n\t\t\t\t\t 8'b0111_1110: num = 5'd14;\n\t\t\t\t\t 8'b1101_1110: num = 5'd15;  \n\t\t\t\t  endcase\n\t\t\t\t  begin\n\t\t\t\t  \tout=out\u003c\u003c4;\n\t\t\t\t\tout[3:0] = num[3:0];\t\n\t\t\t\t  end\n\t\t\t\t  //我不知道为什么必须要用begin end把赋值语句框住。我做的时候没有框住就出不来。\n\t\t\tend\n\t\t\tend\n\t\t\nend\nendmodule   \n```\n\n\u003e ## 2.3 将键盘输入转换为操作数的中间键\n\n```Verilog\nmodule midware(\n\tinput [15:0]key_out,\n\toutput wire [7:0] X,\n\toutput wire [7:0] Y\n);\n\tassign X=key_out[15:8];\n\tassign Y=key_out[7:0];\nendmodule\n\n```\n\n\u003e ## 2.4 8位7段数码管\n\n```Verilog\nmodule segment_displays(clk,N,seg,sel);\n\tinput clk;\n\tinput [31:0] N;\n\toutput reg [7:0] seg;\n\toutput reg [2:0] sel;\n\treg [3:0]num;\n\talways@(posedge clk)\n\tbegin\n\t\tsel\u003c=sel+1;\n\t\tcase(sel)\n\t\t\t3'b110:num\u003c=N[3:0];\n\t\t\t3'b101:num\u003c=N[7:4];\n\t\t\t3'b100:num\u003c=N[11:8];\n\t\t\t3'b011:num\u003c=N[15:12];\n\t\t\t3'b010:num\u003c=N[19:16];\n\t\t\t3'b001:num\u003c=N[23:20];\n\t\t\t3'b000:num\u003c=N[27:24];\n\t\t\t3'b111:num\u003c=N[31:28];\n\t\tendcase\n\tend\n\talways@(num)\n\tbegin\n\t\tcase(num)\n\t\t\t4'b0000:seg\u003c=8'b00111111;\t//\"0\"\n\t\t\t4'b0001:seg\u003c=8'b00000110;\t//\"1\"\n\t\t\t4'b0010:seg\u003c=8'b01011011;\t//\"2\"\n\t\t\t4'b0011:seg\u003c=8'b01001111;\t//\"3”\n\t\t\t4'b0100:seg\u003c=8'b01100110;\t//\"4\"\n\t\t\t4'b0101:seg\u003c=8'b01101101;\t//\"5\"\n\t\t\t4'b0110:seg\u003c=8'b01111101;\t//\"6\"\n\t\t\t4'b0111:seg\u003c=8'b00000111;\t//\"8\"\n\t\t\t4'b1000:seg\u003c=8'b01111111;\t//\"8\"\n\t\t\t4'b1001:seg\u003c=8'b01101111;\t//\"9\"\n\t\t\t4'b1010:seg\u003c=8'b01110111;\t//\"A\"\n\t\t\t4'b1011:seg\u003c=8'b01111100;\t//\"b\"\n\t\t\t4'b1100:seg\u003c=8'b00111001;\t//\"c\"\n\t\t\t4'b1101:seg\u003c=8'b01011110;\t//\"d\"\n\t\t\t4'b1110:seg\u003c=8'b01111001;\t//\"E\"\n\t\t\t4'b1111:seg\u003c=8'b01110001;\t//\"F\"\n\t\t\tdefault:seg\u003c=8'b00000000;\t//\"dark\"\n\t\tendcase\n\tend\nendmodule\n```\n\n\n\u003e # 3 引脚分配\n\n\u003cimg src=\"/images/pin3.png\" width=\"80%\"\u003e\n\n\u003e # 4 仿真波形\n\n\n\n\u003cimg src=\"/images/wvf3.png\" width=\"80%\"\u003e\n\n\u003cimg src=\"/images/wvf3_1.png\" width=\"80%\"\u003e\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fseptemus%2Fswjtu_computer_organization_exp3_multiply","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fseptemus%2Fswjtu_computer_organization_exp3_multiply","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fseptemus%2Fswjtu_computer_organization_exp3_multiply/lists"}