{"id":28220420,"url":"https://github.com/septemus/swjtu_computer_organization_exp_1_4digit_adder","last_synced_at":"2026-02-26T06:27:16.321Z","repository":{"id":152726221,"uuid":"626955790","full_name":"Septemus/swjtu_computer_organization_exp_1_4digit_adder","owner":"Septemus","description":"西南交通大学计组实验1-四位加法器设计","archived":false,"fork":false,"pushed_at":"2024-04-09T05:48:55.000Z","size":1865,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-10-30T20:51:04.615Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Septemus.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2023-04-12T13:49:30.000Z","updated_at":"2025-05-27T10:36:00.000Z","dependencies_parsed_at":"2024-04-09T06:46:19.529Z","dependency_job_id":null,"html_url":"https://github.com/Septemus/swjtu_computer_organization_exp_1_4digit_adder","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Septemus/swjtu_computer_organization_exp_1_4digit_adder","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp_1_4digit_adder","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp_1_4digit_adder/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp_1_4digit_adder/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp_1_4digit_adder/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Septemus","download_url":"https://codeload.github.com/Septemus/swjtu_computer_organization_exp_1_4digit_adder/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Septemus%2Fswjtu_computer_organization_exp_1_4digit_adder/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29850043,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-25T22:37:40.667Z","status":"online","status_checked_at":"2026-02-26T02:00:06.774Z","response_time":89,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-05-18T04:15:21.942Z","updated_at":"2026-02-26T06:27:16.303Z","avatar_url":"https://github.com/Septemus.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003e # 0 关于\n\n欢迎到我的博客文章查看更多内容😄：\n[https://septemus.github.io/computer_organization_exp1/\n](https://septemus.github.io/computer_organization_exp1/)\n\u003e # 1 实验内容\n\n设计四位加法器\n\n\u003e # 2 代码/原理图\n\n\u003e ## 2.1 顶层文件\n\n\u003cimg src=\"/images/exp1block.png\" width=\"70%\"\u003e\n\n\u003e ## 2.2 全加器\n\n```Verilog\nmodule full_adder(a,b,c0,s,c1);\n\tinput a,b,c0;\n\toutput wire s,c1;\n\twire tmp1,tmp2,tmp3;\n\thalf_adder ha1(a,b,tmp1,tmp2);\n\thalf_adder ha2(tmp1,c0,s,tmp3);\n\tassign c1=tmp2|tmp3;\nendmodule\n```\n\n\u003e ## 2.3 半加器\n\n```Verilog\nmodule half_adder(a,b,s,c);\n\tinput a,b;\n\toutput wire s,c;\n\tassign s=a^b;\n\tassign c=a\u0026b;\nendmodule\n```\n\n\u003e ## 2.4 7段数码管译码器\n\n```Verilog\nmodule segment_displays(num,seg);\n\tinput [3:0] num;\n\toutput reg [7:0] seg;\n\talways@(num)\n\tbegin\n\t\tcase(num)\n\t\t\t4'b0000:seg\u003c=8'b00111111;\t//\"0\"\n\t\t\t4'b0001:seg\u003c=8'b00000110;\t//\"1\"\n\t\t\t4'b0010:seg\u003c=8'b01011011;\t//\"2\"\n\t\t\t4'b0011:seg\u003c=8'b01001111;\t//\"3”\n\t\t\t4'b0100:seg\u003c=8'b01100110;\t//\"4\"\n\t\t\t4'b0101:seg\u003c=8'b01101101;\t//\"5\"\n\t\t\t4'b0110:seg\u003c=8'b01111101;\t//\"6\"\n\t\t\t4'b0111:seg\u003c=8'b00000111;\t//\"8\"\n\t\t\t4'b1000:seg\u003c=8'b01111111;\t//\"8\"\n\t\t\t4'b1001:seg\u003c=8'b01101111;\t//\"9\"\n\t\t\t4'b1010:seg\u003c=8'b01110111;\t//\"A\"\n\t\t\t4'b1011:seg\u003c=8'b01111100;\t//\"b\"\n\t\t\t4'b1100:seg\u003c=8'b00111001;\t//\"c\"\n\t\t\t4'b1101:seg\u003c=8'b01011110;\t//\"d\"\n\t\t\t4'b1110:seg\u003c=8'b01111001;\t//\"E\"\n\t\t\t4'b1111:seg\u003c=8'b01110001;\t//\"F\"\n\t\t\tdefault:seg\u003c=8'b00111111;\t//\"0\"\n\t\tendcase\n\tend\nendmodule\n```\n\u003e # 3 引脚分配\n\n\u003cimg src=\"/images/pin1.png\" width=\"80%\"\u003e\n\n\u003e # 4 仿真波形\n\n\u003cimg src=\"/images/wvf1.png\" width=\"80%\"\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fseptemus%2Fswjtu_computer_organization_exp_1_4digit_adder","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fseptemus%2Fswjtu_computer_organization_exp_1_4digit_adder","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fseptemus%2Fswjtu_computer_organization_exp_1_4digit_adder/lists"}