{"id":46893364,"url":"https://github.com/sercanarga/pcileechgen","last_synced_at":"2026-05-12T00:03:54.211Z","repository":{"id":341114897,"uuid":"1168925584","full_name":"sercanarga/PCILeechGen","owner":"sercanarga","description":"PCILeech firmware generator tool","archived":false,"fork":false,"pushed_at":"2026-04-26T23:27:35.000Z","size":926,"stargazers_count":31,"open_issues_count":4,"forks_count":12,"subscribers_count":2,"default_branch":"main","last_synced_at":"2026-04-26T23:28:50.357Z","etag":null,"topics":["dma","firmware","pcie","pcileech","pcileech-dma","pcileech-fpga"],"latest_commit_sha":null,"homepage":"https://sercanarga.github.io/PCILeechGen/","language":"Go","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"cc0-1.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/sercanarga.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":".github/FUNDING.yml","license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null},"funding":{"github":"sercanarga"}},"created_at":"2026-02-28T00:29:15.000Z","updated_at":"2026-04-26T23:26:15.000Z","dependencies_parsed_at":"2026-03-10T23:00:44.927Z","dependency_job_id":null,"html_url":"https://github.com/sercanarga/PCILeechGen","commit_stats":null,"previous_names":["sercanarga/pcileechgen"],"tags_count":91,"template":false,"template_full_name":null,"purl":"pkg:github/sercanarga/PCILeechGen","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sercanarga%2FPCILeechGen","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sercanarga%2FPCILeechGen/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sercanarga%2FPCILeechGen/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sercanarga%2FPCILeechGen/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/sercanarga","download_url":"https://codeload.github.com/sercanarga/PCILeechGen/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sercanarga%2FPCILeechGen/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":32318417,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-26T23:26:28.701Z","status":"ssl_error","status_checked_at":"2026-04-26T23:26:25.802Z","response_time":129,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["dma","firmware","pcie","pcileech","pcileech-dma","pcileech-fpga"],"created_at":"2026-03-10T23:00:30.314Z","updated_at":"2026-04-27T01:02:06.445Z","avatar_url":"https://github.com/sercanarga.png","language":"Go","funding_links":["https://github.com/sponsors/sercanarga"],"categories":[],"sub_categories":[],"readme":"\u003e [!CAUTION]\n\u003e This tool is provided for **educational and research purposes only**. The authors do not condone or encourage the use of this software for cheating, circumventing anti-cheat systems, or any other activity that violates terms of service of any software or platform. Users are solely responsible for ensuring their use of this tool complies with all applicable laws and agreements.\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"https://raw.githubusercontent.com/sercanarga/PCILeechGen/main/docs/logo.png\" alt=\"PCILeechGen\" width=\"200\"\u003e\n\u003c/p\u003e\n\n\u003ch1 align=\"center\"\u003ePCILeechGen\u003c/h1\u003e\n\n\u003cp align=\"center\"\u003e\n  \u003cstrong\u003eCustom firmware generator for \u003ca href=\"https://github.com/ufrisk/pcileech-fpga\"\u003ePCILeech FPGA\u003c/a\u003e boards\u003c/strong\u003e\u003cbr\u003e\n  Reads a real PCI/PCIe donor device via VFIO, clones its complete identity including config space, BARs, and capabilities, and builds a ready-to-flash \u003ccode\u003e.bin\u003c/code\u003e firmware through Vivado.\n\u003c/p\u003e\n\n\u003cp align=\"center\"\u003e\n  \u003ca href=\"https://github.com/sercanarga/PCILeechGen/actions/workflows/codeql.yml\"\u003e\u003cimg src=\"https://github.com/sercanarga/PCILeechGen/actions/workflows/codeql.yml/badge.svg\" alt=\"CodeQL\"\u003e\u003c/a\u003e\n  \u003ca href=\"https://github.com/sercanarga/PCILeechGen/actions/workflows/ci.yml\"\u003e\u003cimg src=\"https://img.shields.io/endpoint?url=https://gist.githubusercontent.com/sercanarga/b85bf5ab915f0f64fc15df8d52b8924c/raw\" alt=\"Coverage\"\u003e\u003c/a\u003e\n  \u003ca href=\"https://goreportcard.com/report/github.com/sercanarga/pcileechgen\"\u003e\u003cimg src=\"https://goreportcard.com/badge/github.com/sercanarga/pcileechgen\" alt=\"Go Report Card\"\u003e\u003c/a\u003e\n  \u003ca href=\"https://go.dev/\"\u003e\u003cimg src=\"https://img.shields.io/github/go-mod/go-version/sercanarga/PCILeechGen\" alt=\"Go\"\u003e\u003c/a\u003e\n  \u003ca href=\"https://github.com/sercanarga/PCILeechGen/blob/main/LICENSE\"\u003e\u003cimg src=\"https://img.shields.io/badge/License-CC0_1.0-lightgrey.svg\" alt=\"License: CC0-1.0\"\u003e\u003c/a\u003e\n  \u003ca href=\"https://discord.gg/kcWVCAhNSg\"\u003e\u003cimg src=\"https://img.shields.io/discord/1477751220037877881?logo=discord\u0026logoColor=white\u0026label=Discord\u0026color=5865F2\" alt=\"Discord\"\u003e\u003c/a\u003e\n\u003c/p\u003e\n\n\n## Contents\n\n- [Features](#features)\n- [How It Works](#how-it-works)\n- [Supported Boards](#supported-boards)\n- [Quick Start](#quick-start)\n- [Commands](#commands)\n- [Utilities](#utilities)\n- [Output](#output)\n- [Architecture](#architecture)\n- [Development](#development)\n- [Special Thanks](#special-thanks)\n- [License](#license)\n\n\n## Features\n\n\u003ctable\u003e\n\u003ctr\u003e\u003ctd valign=\"top\"\u003e\n\n**Device Identity Cloning**\n- Vendor / Device / Revision ID\n- Subsystem Vendor / Device ID\n- Class Code (base, sub-class, interface)\n- Device Serial Number (stripped when absent from donor)\n\n\u003c/td\u003e\u003ctd valign=\"top\"\u003e\n\n**BAR Emulation**\n- BAR0 Layout (type, size, 32/64-bit)\n- BAR Content Emulation (donor memory snapshot)\n- NVMe CC-\u003eCSTS State Machine\n- NVMe Admin Queue Responder (Identify, Set/Get Features, Create IO CQ/SQ)\n- NVMe DMA Bridge (admin queue doorbell + completion)\n- xHCI USBCMD/USBSTS State Machine\n- Auto-bind VFIO on BAR read failure\n- Unreliable probe data detection (0xFF rejection)\n- BAR size power-of-2 rounding\n- Build-time offset validation\n\n\u003c/td\u003e\u003c/tr\u003e\n\u003ctr\u003e\u003ctd valign=\"top\"\u003e\n\n**Config Space**\n- Full 4KB shadow + scrubbing pipeline (17 passes)\n- Per-register write masks (PM/PCIe lock, SlotCtl, DevCtl2, LinkCtl2, upper 32-bit BAR)\n- PCIe Capability Injection (synthesized PCIe v2 Endpoint for conventional PCI donors)\n- Power Management lock (D-state + NoSoftReset, PMCSR write-protected)\n- Vendor Quirks (Renesas firmware status)\n- Vendor-Specific Capability Preservation (Intel, Realtek, Broadcom, Qualcomm, ASMedia)\n\n\u003c/td\u003e\u003ctd valign=\"top\"\u003e\n\n**Capability Management**\n- Capability Filtering (SR-IOV, Resizable BAR, ATS, L1PM, etc.)\n- Capability Pruning (VPD, AGP, HyperTransport, PCI-X)\n- MSI Vector Count Matching (donor Multiple Message Capable)\n- MSI-X Capability Mirroring (table size, BIR, offsets from donor)\n- MSI-X Table Replication (separate BRAM, donor table + PBA)\n- MSI-X Interrupt Controller (4-state FSM with LFSR jitter)\n\n\u003c/td\u003e\u003c/tr\u003e\n\u003ctr\u003e\u003ctd valign=\"top\"\u003e\n\n**Stealth \u0026 Timing**\n- TLP Latency Emulation (xorshift128+ PRNG, 4-seed, thermal drift, burst correlation)\n- Donor-Profiled TLP Timing (per-device response histogram CDF reproduction)\n- Write Completion Emulation (separate MMIO write latency FSM with wr_ack handshake)\n- Completion Timeout (force-release hung reads with 0xFFFFFFFF after configurable cycles)\n- ASPM Clamping (L0s/L1, Clock PM, and LTR Mechanism disable)\n- AER Mask Normalization (error reporting stealth)\n- Power State Variance (PMC Data Scale jitter per build)\n- Subsystem ID Offset Jitter (±1 random offset, stays within driver tolerance)\n- DSN OUI-Preserving Randomization (valid DSNs keep vendor OUI, serial randomized per build)\n- Link Speed / Width (clamped to board maximum, not donor negotiated speed)\n- P\u0026R Randomization (per-build Vivado placement seed)\n- VSEC Entropy Embed (build-unique fingerprint via VSEC ID=0xFC in extended config space)\n\n\u003c/td\u003e\u003ctd valign=\"top\"\u003e\n\n**Diagnostics \u0026 Validation**\n- VFIO Diagnostics (power state, BAR accessibility, IOMMU isolation)\n- Fallback Config (class-based defaults for NVMe, xHCI, Ethernet, Audio, GPU, SATA, Wi-Fi, Thunderbolt, Generic)\n- Post-Build Validation (output file existence, SV IDs, HEX/COE format)\n- Vivado Build Report (error categorization, benign warning filter)\n- Build Manifest (JSON with SHA256 checksums)\n- Manifest Verification (`verify-manifest` - integrity check)\n- Config Space Diff Report (per-byte change log with reasons)\n- Capability Chain Validation (pointer sanity, loop detection, max depth check)\n\n\u003c/td\u003e\u003c/tr\u003e\n\u003c/table\u003e\n\n\u003e [!TIP]\n\u003e Run `check` before `build` to verify donor device suitability and board compatibility.\n\n\n\n## How It Works\n\n```mermaid\nflowchart LR\n    A[\"scan\"] --\u003e B[\"check\"]\n    B --\u003e C[\"build\"]\n    C --\u003e D[\"flash\"]\n\n    A -.- A1[\"Enumerate PCI devices\u003cbr\u003eDetect VFIO status\"]\n    B -.- B1[\"Validate donor device\u003cbr\u003eRead config space \u0026 BARs\"]\n    C -.- C1[\"Clone identity -\u003e Generate SV/COE/TCL\u003cbr\u003e-\u003e Vivado synthesis -\u003e .bin\"]\n    D -.- D1[\"Flash bitstream\u003cbr\u003eto FPGA board\"]\n```\n\n---\n\n## Supported Boards\n\n| Board | FPGA | Lanes | Form Factor |\n|:------|:-----|:-----:|:-----------:|\n| [CaptainDMA_M2_x1](https://github.com/ufrisk/pcileech-fpga/tree/master/CaptainDMA) | XC7A35T-325 | x1 | M.2 |\n| [CaptainDMA_M2_x4](https://github.com/ufrisk/pcileech-fpga/tree/master/CaptainDMA) | XC7A35T-325 | x4 | M.2 |\n| [CaptainDMA_35T](https://github.com/ufrisk/pcileech-fpga/tree/master/CaptainDMA) | XC7A35T-484 | x1 | PCIe |\n| [CaptainDMA_75T](https://github.com/ufrisk/pcileech-fpga/tree/master/CaptainDMA) | XC7A75T-484 | x1 | PCIe |\n| [CaptainDMA_100T](https://github.com/ufrisk/pcileech-fpga/tree/master/CaptainDMA) | XC7A100T-484 | x1 | PCIe |\n| [ScreamerM2](https://github.com/ufrisk/pcileech-fpga/tree/master/ScreamerM2) | XC7A35T-325 | x1 | M.2 |\n| [pciescreamer](https://github.com/ufrisk/pcileech-fpga/tree/master/pciescreamer) | XC7A35T-484 | x1 | PCIe |\n| [NeTV2_35T](https://github.com/ufrisk/pcileech-fpga/tree/master/NeTV2) | XC7A35T-484 | x1 | M.2 |\n| [NeTV2_100T](https://github.com/ufrisk/pcileech-fpga/tree/master/NeTV2) | XC7A100T-484 | x1 | M.2 |\n| [PCIeSquirrel](https://github.com/ufrisk/pcileech-fpga/tree/master/PCIeSquirrel) | XC7A35T-484 | x1 | PCIe |\n| [EnigmaX1](https://github.com/ufrisk/pcileech-fpga/tree/master/EnigmaX1) | XC7A75T-484 | x1 | M.2 |\n| [ZDMA](https://github.com/ufrisk/pcileech-fpga/tree/master/ZDMA) | XC7A100T-484 | x4 | PCIe |\n| [GBOX](https://github.com/ufrisk/pcileech-fpga/tree/master/GBOX) | XC7A35T-484 | x1 | Mini PCIe |\n| [ac701_ft601](https://github.com/ufrisk/pcileech-fpga/tree/master/ac701_ft601) | XC7A200T-676 | x4 | Dev Board |\n| [acorn](https://github.com/ufrisk/pcileech-fpga/tree/master/acorn_ft2232h) | XC7A200T-484 | x4 | M.2 |\n| [litefury](https://github.com/ufrisk/pcileech-fpga/tree/master/ZDMA) | XC7A100T-484 | x4 | M.2 |\n| [sp605_ft601](https://github.com/ufrisk/pcileech-fpga/tree/master/sp605_ft601) | XC6SLX45T-484 | x1 | Dev Board |\n\n---\n\n## Quick Start\n\n### Prerequisites\n\n- **Go** 1.26+\n- **Linux** with IOMMU/VFIO enabled\n- **Vivado** 2023.2+ (for synthesis)\n\n\u003e [!NOTE]\n\u003e VFIO requires IOMMU to be enabled in BIOS and kernel parameters (`intel_iommu=on` or `amd_iommu=on`).\n\n### Installation\n\n```bash\ngit clone --recurse-submodules https://github.com/sercanarga/PCILeechGen.git\ncd PCILeechGen \u0026\u0026 make build\n```\n\n\u003e [!IMPORTANT]\n\u003e The `--recurse-submodules` flag is required to fetch the pcileech-fpga library.\n\n### Usage\n\n```bash\n# 1. Scan for available PCI devices\nsudo ./bin/pcileechgen scan\n\n# 2. Check if a device is suitable as donor\nsudo ./bin/pcileechgen check --bdf 0000:02:00.0\n\n# 3. Build firmware\nsudo ./bin/pcileechgen build --bdf 0000:03:00.0 --board CaptainDMA_100T\n```\n\n---\n\n## Commands\n\n### `scan` - List PCI Devices\n\nShows all PCI devices with VFIO compatibility status.\n\n```bash\nsudo ./bin/pcileechgen scan\n```\n\n\u003cdetails\u003e\n\u003csummary\u003eExample output\u003c/summary\u003e\n\n```\n0000:00:00.0 Host bridge [0600]: Intel Corporation Xeon E3-1200 v6/7th Gen Core Processor Host Bridge [8086:591f]\n0000:00:17.0 SATA controller [0106]: Intel Corporation 200 Series PCH SATA controller [8086:a282]\n0000:01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GP106 [GeForce GTX 1060 3GB] [10de:1c02] [WARN] group(3)\n0000:02:00.0 Audio device [0403]: Creative Labs CA0132 Sound Core3D [1102:0012] [OK] vfio\n\nTotal: 16 devices\n```\n\n\u003c/details\u003e\n\n### `check` - Verify Donor Device\n\nRuns a full diagnostic on a device to verify donor suitability.\n\n```bash\nsudo ./bin/pcileechgen check --bdf 0000:02:00.0\n```\n\n\u003cdetails\u003e\n\u003csummary\u003eExample output\u003c/summary\u003e\n\n```\nChecking device 0000:02:00.0...\n\n[OK] Device found: 1102:0012 Audio device\n[OK] Config space readable: 4096 bytes\n[OK] IOMMU is enabled\n[OK] VFIO modules loaded\n[OK] IOMMU group: 9\n[OK] Device is alone in its IOMMU group\n[OK] Power state: D0 (active)\n[OK] Already bound to vfio-pci\n\nCapabilities (3):\n  [01] Power Management at offset 0x50\n  [05] MSI at offset 0x60\n  [10] PCI Express at offset 0x70\n\nExtended Capabilities (4):\n  [0001] Advanced Error Reporting at offset 0x100\n  [0003] Device Serial Number at offset 0x150\n  [0010] Single Root I/O Virtualization at offset 0x180\n  [0002] VC at offset 0x260\n\nBARs:\n  BAR0: Memory32 at 0xfe800000, size 16 KiB [accessible]\n\n--- Board Compatibility ---\nDonor Link: 2.5 GT/s x1\nDonor DSN:  0x0123456789abcdef\n\nCompatible boards:\n  PCIeSquirrel           xc7a35tfgg484-2 x1 (exact match)\n  CaptainDMA_100T        xc7a100tfgg484-2 x1 (exact match)\n  ...\n\nTotal: 17 boards\n\n--- Summary ---\n[OK] Device is ready for firmware generation\n```\n\n\u003c/details\u003e\n\n### `build` - Generate Firmware\n\nGenerates firmware artifacts and optionally runs Vivado synthesis.\n\n```bash\n# Full build (artifacts + Vivado synthesis)\nsudo ./bin/pcileechgen build --bdf 0000:03:00.0 --board CaptainDMA_100T\n\n# Artifacts only (no Vivado)\nsudo ./bin/pcileechgen build --bdf 0000:03:00.0 --board CaptainDMA_100T --skip-vivado\n\n# Offline build from saved JSON\nsudo ./bin/pcileechgen build --from-json device_context.json --board CaptainDMA_100T --skip-vivado\n```\n\n\u003e [!WARNING]\n\u003e Full synthesis may take 30-60 minutes depending on FPGA size. Use `--skip-vivado` to generate only artifacts.\n\n\u003cdetails\u003e\n\u003csummary\u003eAll flags\u003c/summary\u003e\n\n| Flag | Default | Description |\n|:-----|:--------|:------------|\n| `--bdf` | - | Donor device BDF address |\n| `--board` | - | Target FPGA board **(required)** |\n| `--from-json` | - | Load donor data from JSON (offline build) |\n| `--output` | `pcileech_datastore` | Output directory |\n| `--lib-dir` | `lib/pcileech-fpga` | Path to pcileech-fpga library |\n| `--skip-vivado` | `false` | Only generate artifacts, skip synthesis |\n| `--stock-bar` | `false` | Skip custom BAR module generation (uses stock pcileech-fpga BAR controller) diagnostic flag for isolating detection issues |\n| `--vivado-path` | auto-detect | Path to Vivado installation |\n| `--jobs` | `4` | Parallel Vivado jobs |\n| `--timeout` | `3600` | Vivado timeout (seconds) |\n\n\u003c/details\u003e\n\n### `validate` - Verify Artifacts\n\nVerifies generated artifacts match the donor device context.\n\n```bash\n./bin/pcileechgen validate --json device_context.json --output-dir pcileech_datastore/\n./bin/pcileechgen validate --json device_context.json --board PCIeSquirrel  # exact build match\n```\n\n\u003e Checks include: output file existence, vendor/device ID presence in SV, HEX line format, COE structure.\n\n### `verify-manifest` - Verify Build Integrity\n\nChecks that all build artifacts match their SHA256 checksums in the manifest.\n\n```bash\n./bin/pcileechgen verify-manifest --manifest pcileech_datastore/build_manifest.json --output-dir pcileech_datastore/\n```\n\n### `version` - Print Version\n\n```bash\n./bin/pcileechgen version\n```\n\n### `boards` - List Supported Boards\n\n```bash\n./bin/pcileechgen boards\n```\n\n\u003cdetails\u003e\n\u003csummary\u003eExample output\u003c/summary\u003e\n\n```\nNAME              FPGA PART          PCIe  TOP MODULE\n----              ---------          ----  ----------\nPCIeSquirrel      xc7a35tfgg484-2    x1    pcileech_squirrel_top\nScreamerM2        xc7a35tcsg325-2    x1    pcileech_screamer_m2_top\nCaptainDMA_100T   xc7a100tfgg484-2   x1    pcileech_100t484_x1_top\nZDMA              xc7a100tfgg484-2   x4    pcileech_tbx4_100t_top\n...\n\nTotal: 17 boards\n```\n\n\u003c/details\u003e\n\n---\n\n## Utilities\n\n### Windows Device History Cleanup\n\nAfter flashing and testing firmware, Windows caches device metadata in the registry. Stale entries from previous firmware builds can cause conflicts, Code 10 errors, or driver misidentification. The `tools/` directory contains an interactive cleanup utility:\n\n| File | Description |\n|:-----|:-----------|\n| `cleanup_device_history.bat` | Windows batch launcher (double-click, runs as Administrator) |\n| `cleanup_device_history.ps1` | PowerShell script with interactive arrow-key menu |\n\n**Usage:**\n- **Double-click** `cleanup_device_history.bat` and confirm UAC prompt\n- Or open PowerShell as Administrator and run: `.\\cleanup_device_history.ps1`\n\n\u003e [!TIP]\n\u003e If running the `.ps1` directly and you get an execution policy error, use: `powershell -ExecutionPolicy Bypass -File .\\cleanup_device_history.ps1`\n\n**Features:**\n- Scans both PCI (`Enum\\PCI`) and USB (`Enum\\USB`) device history across all ControlSets\n- Deduplicates by Hardware ID + Instance ID, merging multi-ControlSet entries\n- Interactive menu with arrow key navigation, driver info, and device type tags `[PCI]`/`[USB]`\n- Automatic registry backup to desktop before any changes\n- Cleans setupapi logs, DeviceMetadataStore, PnP event logs, and device migration cache\n\n\u003e [!IMPORTANT]\n\u003e Requires Administrator privileges. Reboot after cleanup before reconnecting the device.\n\n---\n\n## Output\n\nThe build command generates the following directory structure:\n\n```\npcileech_datastore/\n├── device_context.json                  # Donor device snapshot\n├── pcileech_cfgspace.coe                # 4KB config space (scrubbed)\n├── pcileech_cfgspace_writemask.coe      # Per-register write masks\n├── pcileech_bar_zero4k.coe             # BAR0 content snapshot\n├── pcileech_bar_impl_device.sv         # BAR implementation (register-level)\n├── pcileech_tlps128_bar_controller.sv  # TLP BAR controller\n├── pcileech_msix_table.sv              # MSI-X table + PBA emulation\n├── pcileech_nvme_admin_responder.sv    # NVMe admin queue FSM (if NVMe)\n├── pcileech_nvme_dma_bridge.sv        # NVMe DMA bridge (if NVMe)\n├── tlp_latency_emulator.sv            # Response latency emulation\n├── device_config.sv                    # Device identity + feature flags\n├── config_space_init.hex               # Config space init ($readmemh)\n├── msix_table_init.hex                 # MSI-X table init ($readmemh)\n├── identify_init.hex                   # NVMe Identify ROM (if NVMe)\n├── scrub_diff_report.txt               # Config space change log (per-byte)\n├── build_manifest.json                 # File checksums + build metadata\n├── vivado_generate_project.tcl         # Project creation script\n├── vivado_build.tcl                    # Synthesis script\n├── src/                                # Patched board SV sources\n└── *.bin                               # Bitstream (after Vivado)\n```\n\n---\n\n## Architecture\n\n```\ncmd/pcileechgen/              CLI entry point\n│                             scan, check, build, validate, verify-manifest, boards, version\n│\ninternal/\n├── board/                    Board registry (embedded JSON, 17 boards)\n├── donor/                    VFIO device reader + BAR profiling\n├── pci/                      Config space parser, capabilities, MSI-X\n├── firmware/\n│   ├── scrub/                Config space scrubbing (17-pass pipeline)\n│   ├── barmodel/             BAR register model (spec + profiled)\n│   ├── svgen/                SV code generation (embedded .sv.tmpl templates)\n│   ├── nvme/                 NVMe Identify data generation\n│   ├── tclgen/               Vivado TCL script generation\n│   ├── devclass/             Device class strategy (NVMe, xHCI, Ethernet, Audio, GPU, SATA, Wi-Fi, Thunderbolt)\n│   ├── fallback/             Class-based fallback config (when probe data is unavailable)\n│   ├── output/               Artifact writer (SV pipeline + COE + HEX)\n│   ├── overlay/              Byte-level diff tracking\n│   ├── variance/             Config space randomization\n│   └── codegen/              HEX/COE formatters\n└── vivado/                   Vivado process runner\n```\n\n## Development\n\n```bash\nmake test             # Run all tests\nmake test-coverage    # Run tests with coverage report\nmake lint             # Run linter\nmake check            # Run vet + lint + test (all checks)\n```\n\n## Special Thanks\n\n- **[pcileech-fpga](https://github.com/ufrisk/pcileech-fpga)** by Ulf Frisk - the FPGA framework this project builds upon\n- **[CaptainDMA](https://captaindma.com)** - for best FPGA DMA hardware\n\n## License\n\n[Creative Commons Zero v1.0 Universal](https://github.com/sercanarga/PCILeechGen/blob/main/LICENSE)","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsercanarga%2Fpcileechgen","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsercanarga%2Fpcileechgen","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsercanarga%2Fpcileechgen/lists"}