{"id":21876959,"url":"https://github.com/sergz72/fpga","last_synced_at":"2025-07-06T14:03:28.671Z","repository":{"id":246901860,"uuid":"824641930","full_name":"sergz72/FPGA","owner":"sergz72","description":"FPGA related stuff","archived":false,"fork":false,"pushed_at":"2025-07-04T16:52:54.000Z","size":1326,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-07-06T14:02:29.459Z","etag":null,"topics":["assembler","assembly-language","bytecode-compiler","cpu","cyclone","forth","forth-cpu","forth-language","fpga","fpga-programming","gowin","java","java-cpu","risc-v","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/sergz72.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2024-07-05T15:21:23.000Z","updated_at":"2025-07-04T16:52:57.000Z","dependencies_parsed_at":"2024-11-03T09:23:03.758Z","dependency_job_id":"a4226f5d-2413-49e6-8877-cd66a5d1d6ea","html_url":"https://github.com/sergz72/FPGA","commit_stats":null,"previous_names":["sergz72/fpga"],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/sergz72/FPGA","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sergz72%2FFPGA","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sergz72%2FFPGA/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sergz72%2FFPGA/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sergz72%2FFPGA/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/sergz72","download_url":"https://codeload.github.com/sergz72/FPGA/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sergz72%2FFPGA/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":263914030,"owners_count":23529074,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembler","assembly-language","bytecode-compiler","cpu","cyclone","forth","forth-cpu","forth-language","fpga","fpga-programming","gowin","java","java-cpu","risc-v","verilog"],"created_at":"2024-11-28T08:07:25.331Z","updated_at":"2025-07-06T14:03:28.620Z","avatar_url":"https://github.com/sergz72.png","language":"Verilog","readme":"# FPGA projects\n\n[Multidevice](multidevice) - Multidevice module for [Universal measurements tool](https://github.com/sergz72/ARM/tree/master/meter_ui).\n\n[Cpu16Lite](Cpu16Lite) - 16 bit cpu with 256 registers.\n\n[ForthCPU](ForthCPU) - CPU, designed to run code, compiled by Forth language compiler.\n\n[JavaCPU](JavaCPU) - CPU, designed to run code, translated from Java bytecode.\n\n[LedPmodTest](LedPmodTest) - simple Verilog code to test LED PMODs.\n\n[Software](Software) - Various software related to my FPGA projects (compilers, translators, etc...).\n\n[Tiny16](tiny16) - 16 bit cpu.\n\n[Tiny32](tiny32) - RV32I(M) core.\n\n[archived](archived) - archived projects.\n\n[boards](boards) - projects, related to specific FPGA boards.\n\n[common](common) - common Verilog components.\n\n[unfinished](unfinished) - unfinished projects.\n\n[untested](untested) - some untested stuff.\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsergz72%2Ffpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsergz72%2Ffpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsergz72%2Ffpga/lists"}