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This implementation is independent of the platform and can be integrated into any design.  \n\n- **PUF:** Implemenation of the Arbiter PUF using Programmable Delay Lines. The target platform is Virtex-6.\n  \n- **TRNG_RO:** Chellenge generator based on RO based TRNG. This implementation is independent of the platform and can be integrated into any design.\n  \n- **MAT_SIM:** Matlab simulation files\n  \n- **ZippedISEProjectVirtex6:** Complete ISE project to run test on PUF. The target platform is Virtex-6. It uses [Simple Interface for Reconfigurable Computing (SIRC)](https://www.microsoft.com/en-us/download/details.aspx?id=52527) [3] to transfer test results to the computer. \n\n\n## References\n[1] Hussain, Siam U., Mehrdad Majzoobi, and Farinaz Koushanfar. \"A built-in-self-test scheme for online evaluation of physical unclonable functions and true random number generators.\" IEEE Transactions on Multi-Scale Computing Systems 2.1 (2016): 2-16.\n\n[2] Rukhin, Andrew, et al. A statistical test suite for random and pseudorandom number generators for cryptographic applications. Booz-Allen and Hamilton Inc Mclean Va, 2001.\n\n[3] Eguro, Ken. \"SIRC: An extensible reconfigurable computing communication API.\" Field-Programmable Custom Computing Machines (FCCM), 2010 18th IEEE Annual International Symposium on. IEEE, 2010.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsiamumar%2Fbist_puf_trng","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsiamumar%2Fbist_puf_trng","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsiamumar%2Fbist_puf_trng/lists"}