{"id":20261785,"url":"https://github.com/sid911/x16bitemulation","last_synced_at":"2025-12-01T15:01:41.764Z","repository":{"id":102074740,"uuid":"334070234","full_name":"Sid911/x16BitEmulation","owner":"Sid911","description":"This repository is basically me trying to emulate 6502 processor which is 16 bit fully on software level.","archived":false,"fork":false,"pushed_at":"2021-11-30T04:55:45.000Z","size":35487,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-03T18:49:49.925Z","etag":null,"topics":["cpp","emulation","processor-simulator"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Sid911.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-01-29T07:31:17.000Z","updated_at":"2021-11-30T04:55:48.000Z","dependencies_parsed_at":null,"dependency_job_id":"e3e77c51-66cb-4f8b-bd3e-85d4db24af65","html_url":"https://github.com/Sid911/x16BitEmulation","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Sid911/x16BitEmulation","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Sid911%2Fx16BitEmulation","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Sid911%2Fx16BitEmulation/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Sid911%2Fx16BitEmulation/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Sid911%2Fx16BitEmulation/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Sid911","download_url":"https://codeload.github.com/Sid911/x16BitEmulation/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Sid911%2Fx16BitEmulation/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":27432590,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-12-01T02:00:06.371Z","response_time":60,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpp","emulation","processor-simulator"],"created_at":"2024-11-14T11:27:08.416Z","updated_at":"2025-12-01T15:01:41.749Z","avatar_url":"https://github.com/Sid911.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# x16BitEmulation\nThis repository is basically me trying to emulate 6502 processor which is 16 bit fully on software level at a logical standpoint. This doesn't support any kind of graphical interface.\n## Disclaimer\nThis main goal of this project is to understand how CPUs works by directly emulating one and to debug it by single stepping instructions. The code is meant to be readable and understandable without many comments but more for writing very cohesive testings using Gtest, a lot of things could be done better.\nThe emulator only shows you what's going on under the hood of a 6502 CPU, without displaying stuff graphically.\n\n\u003e This was built on Visual Studio 2019 but has been upgraded to Visual Studio 2022. Retargeting the solution shouldn't cause any issues because of very less dependencies (only nuget package for Google test is required which should be automatically installed).\n\n![image](https://user-images.githubusercontent.com/27860105/143931641-c1876b47-4092-4b67-9ad7-5b44031f107b.png)\n\n___________\n\n### Currently supported intructions\n\n#### Load/Store Operations\nThese instructions transfer a single byte between memory and one of the registers. Load operations set the negative (N) and zero (Z) flags depending on the value of transferred. Store operations do not affect the flag settings.\n\nDone |Code | Full Form | Flags Changed\n----- | ---- | ------------- | -------------\nYes   | LDA |\tLoad Accumulator | N,Z\nYes   | LDX\t| Load X Register |\tN,Z\nYes    | LDY |\tLoad Y Register |\tN,Z\nYes    | STA |\tStore Accumulator | None\t \nYes    | STX |\tStore X Register | None\nYes    | STY |\tStore Y Register | None \n\n#### Jumps \u0026 Calls\nThe following instructions modify the program counter causing a break to normal sequential execution. The JSR instruction pushes the old PC onto the stack before changing it to the new location allowing a subsequent RTS to return execution to the instruction after the call.\n\nDone  | Code | Second Header | Flags Changed\n----- | ---- | ------------- | -------------\nYes    | JMP\t| Jump to another location\t| None\nYes   | JSR\t| Jump to a subroutine\t| None\nYes    | RTS\t| Return from subroutine\t| none\n\n#### Register Transfers\nThe contents of the X and Y registers can be moved to or from the accumulator, setting the negative (N) and zero (Z) flags as appropriate.\n\nDone  | Code | Second Header              | Flags Changed\n----- | ---- | -------------------------- | -------------\nYes   | TAX  |\tTransfer accumulator to X |\tN,Z\nYes   | TAY\t |  Transfer accumulator to Y |\tN,Z\nYes   | TXA  |\tTransfer X to accumulator |\tN,Z\nYes   | TYA  |\tTransfer Y to accumulator\t| N,Z\n\n\n#### Stack Operator\nThe 6502 microprocessor supports a 256 byte stack fixed between memory locations $0100 and $01FF. A special 8-bit register, S, is used to keep track of the next free byte of stack space. Pushing a byte on to the stack causes the value to be stored at the current free location (e.g. $0100,S) and then the stack pointer is post decremented. Pull operations reverse this procedure.\n\nThe stack register can only be accessed by transferring its value to or from the X register. Its value is automatically modified by push/pull instructions, subroutine calls and returns, interrupts and returns from interrupts.\nDone  | Code | Second Header                  | Flags Changed\n----- | ---- | ------------------------------ | -------------\nYes   | TSX  | Transfer stack pointer to X\t  |   N,Z\nYes   | TXS\t |Transfer X to stack pointer\t    |   None\nYes   | PHA\t |Push accumulator on stack\t      |   None\nYes   | PHP\t |Push processor status on stack  |   None\nYes   | PLA\t |Pull accumulator from stack\t    |   N,Z\nYes   | PLP\t |Pull processor status from stack|\tAll\n\n\n#### Logical \nThe following instructions perform logical operations on the contents of the accumulator and another value held in memory. The BIT instruction performs a logical AND to test the presence of bits in the memory value to set the flags but does not keep the result.\n\nDone  | Code | Second Header                | Flags Changed\n----- | ---- | ---------------------------- | -------------\nYes   | AND\t |Logical AND\t                  |   N,Z\nYes   | EOR\t |Exclusive OR\t                |   N,Z\nYes   | ORA\t |Logical Inclusive OR\t        |   N,Z\nYes   | BIT\t |Bit Test\t                    |   N,V,Z\n\n#### Arithmetic\nThe arithmetic operations perform addition and subtraction on the contents of the accumulator. The compare operations allow the comparison of the accumulator and X or Y with memory values.\nDone  | Code | Second Header                | Flags Changed\n----- | ---- | ---------------------------- | -------------\nYes   | ADC\t |  Add with Carry\t            | N,V,Z,C\nYes   | SBC\t |  Subtract with Carry\t        | N,V,Z,C\nYes   | CMP\t |  Compare accumulator\t        | N,Z,C\nYes   | CPX\t |  Compare X register\t        | N,Z,C\nYes   | CPY\t |  Compare Y register\t        | N,Z,C\n\n#### Increments \u0026 Decrements\nIncrement or decrement a memory location or one of the X or Y registers by one setting the negative (N) and zero (Z) flags as appropriate,\n\nDone  | Code | Second Header                | Flags Changed\n----- | ---- | ---------------------------- | -------------\nYes   | INC\t |Increment a memory location\t  | N,Z\nYes   | INX\t |Increment the X register\t    | N,Z\nYes   | INY\t |Increment the Y register\t    | N,Z\nYes   | DEC\t |Decrement a memory location\t  | N,Z\nYes   | DEX\t |Decrement the X register\t    | N,Z\nYes   | DEY\t |Decrement the Y register\t    | N,Z\n\n\n#### Shifts\n\nShift instructions cause the bits within either a memory location or the accumulator to be shifted by one bit position. The rotate instructions use the contents if the carry flag (C) to fill the vacant position generated by the shift and to catch the overflowing bit. The arithmetic and logical shifts shift in an appropriate 0 or 1 bit as appropriate but catch the overflow bit in the carry flag (C).\n\nDone  | Code | Second Header                | Flags Changed\n----- | ---- | ---------------------------- | -------------\nYes   | ASL\t |  Arithmetic Shift Left\t      | N,Z,C\nYes   | LSR\t |  Logical Shift Right\t        | N,Z,C\nYes   | ROL\t |  Rotate Left\t                | N,Z,C\nYes   | ROR\t |  Rotate Right\t              | N,Z,C\n\n\n#### Branches\n\nBranch instructions break the normal sequential flow of execution by changing the program counter if a specified condition is met. All the conditions are based on examining a single bit within the processor status.\n\nDone  | Code | Second Header                 | Flags Changed\n----- | ---- | ----------------------------- | -------------\nYes   | BCC\t |  Branch if carry flag clear\t | None\nYes   | BCS\t |  Branch if carry flag set\t   | None\nYes   | BEQ\t |  Branch if zero flag set\t     | None\nYes   | BMI\t |  Branch if negative flag set\t | None\nYes   | BNE\t |  Branch if zero flag clear\t   | None\nYes   | BPL\t |  Branch if negative flag clear| None \nYes   | BVC\t |  Branch if overflow flag clear| None\t \n\n\u003e Branch instructions use relative address to identify the target instruction if they are executed. As relative addresses are stored using a signed 8 bit byte the target instruction must be within 126 bytes before the branch or 128 bytes after the branch.\n\n#### Status Flag Changes\n\nThe following instructions change the values of specific status flags.\n\nDone  | Code | Second Header                | Flags Changed\n----- | ---- | ---------------------------- | -------------\nYes   | CLC\t |  Clear carry flag\t          | C\nYes   | CLD\t |  Clear decimal mode flag\t    | D\nYes   | CLI\t |  Clear interrupt disable flag| I\nYes   | CLV\t |  Clear overflow flag\t        | V       \nYes   | SEC\t |  Set carry flag\t            | C\nYes   | SED\t |  Set decimal mode flag\t      | D\nYes   | SEI\t |  Set interrupt disable flag\t| I\n__________\nCurrently the architecture and spec sheet can be found here https://cx16.dk/6502/\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsid911%2Fx16bitemulation","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsid911%2Fx16bitemulation","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsid911%2Fx16bitemulation/lists"}