{"id":13648889,"url":"https://github.com/sifive/chisel-circt","last_synced_at":"2025-04-22T11:33:23.676Z","repository":{"id":37081715,"uuid":"329671813","full_name":"sifive/chisel-circt","owner":"sifive","description":"Library to compile Chisel circuits using LLVM/MLIR (CIRCT)","archived":true,"fork":false,"pushed_at":"2023-03-02T04:37:03.000Z","size":105,"stargazers_count":70,"open_issues_count":0,"forks_count":10,"subscribers_count":18,"default_branch":"main","last_synced_at":"2024-11-09T23:36:24.611Z","etag":null,"topics":["chisel","circt","mlir","scala"],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/sifive.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2021-01-14T16:29:07.000Z","updated_at":"2024-10-11T14:53:18.000Z","dependencies_parsed_at":"2024-01-14T10:59:41.930Z","dependency_job_id":"969bbfe2-36c6-4d09-8788-9ac8d6cdcecb","html_url":"https://github.com/sifive/chisel-circt","commit_stats":null,"previous_names":[],"tags_count":8,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sifive%2Fchisel-circt","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sifive%2Fchisel-circt/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sifive%2Fchisel-circt/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sifive%2Fchisel-circt/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/sifive","download_url":"https://codeload.github.com/sifive/chisel-circt/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250232582,"owners_count":21396664,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","circt","mlir","scala"],"created_at":"2024-08-02T01:04:37.623Z","updated_at":"2025-04-22T11:33:23.360Z","avatar_url":"https://github.com/sifive.png","language":"Scala","funding_links":[],"categories":["Scala"],"sub_categories":[],"readme":"**This project has been upstreamed to [`chipsalliance/chisel`](https://github.com/chipsalliance/chisel).  Any proposed improvements to this repository should be redirected to pull requests on upstream Chisel.**\n\n# chisel-circt\n\n[![Maven Central](https://img.shields.io/maven-central/v/com.sifive/chisel-circt_2.13)](https://maven-badges.herokuapp.com/maven-central/com.sifive/chisel-circt_2.13)\n[![Sonatype Nexus (Snapshots)](https://img.shields.io/nexus/s/com.sifive/chisel-circt_2.13?server=https%3A%2F%2Foss.sonatype.org)](https://oss.sonatype.org/content/repositories/snapshots/com/sifive/chisel-circt_2.13/)\n[![Javadoc](https://javadoc.io/badge2/com.sifive/chisel-circt_2.13/javadoc.svg)](https://javadoc.io/doc/com.sifive/chisel-circt_2.13)\n\n# Compile Chisel using CIRCT/MLIR\n\nThis library provides a `ChiselStage`-like interface for compiling a Chisel circuit using the MLIR-based FIRRTL Compiler (MFC) included in the [llvm/circt](https://github.com/llvm/circt) project.\nThis is an alternative to the Scala-based FIRRTL Compiler (SFC) that Chisel uses by default and is developed in [chipsalliance/firrtl](https://github.com/chipsalliance/firrtl).\n\n**The MFC is a feature complete FIRRTL compiler, but does not support every annotation and custom transform-backed extension to Chisel.**\n\nIf you suspect a CIRCT bug or have questions, you can file an issue on this repository, [post on Discourse](https://llvm.discourse.group/c/Projects-that-want-to-become-official-LLVM-Projects/circt/), or [file an issue on CIRCT](https://github.com/llvm/circt/issues/new/choose).\n\n## Setup\n\nInclude the following in your `build.sbt`.\nSee the badges above for latest release or snapshot version.\n\n``` scala\nlibraryDependencies += \"com.sifive\" %% \"chisel-circt\" % \"X.Y.Z\"\n```\n\nAdditionally, install CIRCT.\nYou can either:\n\n1. Download a release from [`llvm/circt` releases](https://github.com/llvm/circt/releases)\n2. Build and install from [source](https://github.com/llvm/circt)\n\nThis project is compatible with (at least) the released version of CIRCT that it was tested with in CI.\nThis is documented in the release notes of the latest [tag](https://github.com/sifive/chisel-circt/tags).\n\nAfter CIRCT installation is complete, you need `firtool` (the tool provided with CIRCT to compile FIRRTL circuits) on your path so `chisel-circt` can use it.\n\n### Base Project\n\nAlternatively, a base project is provided in [sifive/chisel-circt-demo](https://github.com/sifive/chisel-circt-demo).\n\n## Example\n\nYou can use `circt.stage.ChiselStage` *almost* exactly like `chsel3.stage.ChiselStage`.\nE.g., the following will compile a simple module using CIRCT.\n\n``` scala\nimport chisel3._\n\nclass Foo extends RawModule {\n  val a = IO(Input(Bool()))\n  val b = IO(Output(Bool()))\n\n  b := ~a\n}\n\n/* Note: this is using circt.stage.ChiselStage */\nval verilogString = circt.stage.ChiselStage.emitSystemVerilog(new Foo)\n\nprintln(verilogString)\n/** This will return:\n  *\n  * module Foo(\n  *   input  a,\n  *   output b);\n  *\n  *   assign b = ~a;\n  * endmodule\n  */\n```\n\nThe method `emitSystemVerilog` also accepts parameters for Chisel arguments and Firtool options.\n\nAnother option is using `emitSystemVerilogFile` to generate output files.\nEg. Below the files are created on \"./generated\" directory (passing Chisel args) and without debug source locators (firtool option).\n\n```scala\nChiselStage.emitSystemVerilogFile(\n  new Foo,\n  Array(\"--target-dir\", \"generated\"),\n  Array(\"--strip-debug-info\"),\n)\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsifive%2Fchisel-circt","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsifive%2Fchisel-circt","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsifive%2Fchisel-circt/lists"}