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DUH enables the generation of JSON5 ([duh documents](docs/)) for\ndescribing these components, and also enables export from these documents\nto output deliverables.\n\n## Install\n\nCheck that you have `Node.js` version (12, 14, 16) installed by running:\n\n```\nnode --version\n```\n\nOn [Installing Node.js via package manager](https://nodejs.org/en/download/package-manager/)\n\nInstall `duh` tool suite.\n\n```bash\nnpm i -g duh\n```\n\nYou might need to add `./node_modules/.bin/` to your PATH\n\nIn Bash:\n\n```sh\nexport PATH=./node_modules/.bin:$PATH\n```\n\nAnd test installation with `duh --help`\n\n## Quick start\n\nBase set of DUH tools to author [duh documents](docs/):\n\n* Create\n  - Run `duh init` to create a base document.\n\n* [Import](docs/import.md)\n  - SystemVerilog: Run `duh duh-import-verilog-ports` to import an interface from Verilog RTL of the component\n  - IPXACT: [duh-ipxact](https://github.com/sifive/duh-ipxact)\n\n* Infer\n  - Run `duh-portinf` to infer mappings of portgroups to standard bus\n  definitions AXI, AHB, TileLink, etc.\n  - Run `duh-portbundler` to group ports, which are unassigned to a bus\n  mapping, into structured bundles.\n\n* [Validate](docs/validation.md)\n  - Run `duh validate` to test whether a given document conforms to the\n  DUH document structure.\n\n* [Export](docs/export.md)\n  - Run `duh-export-scala` to generate scala black box wrappers for the\n  component.\n  - IPXACT: [duh-ipxact](https://github.com/sifive/duh-ipxact)\n\n## DUH toolbox\n\n* [duh-scala](https://github.com/sifive/duh-scala) -- Scala / Chisel export\n* [duh-ipxact](https://github.com/sifive/duh-ipxact) -- IP-XACT import / export\n* [duh-systemrdl](https://github.com/sifive/duh-systemrdl) -- SystemRDL import / export\n* [duhportinf](https://github.com/sifive/duhportinf) -- Bus interfaces inference\n* [duh-bus](https://github.com/sifive/duh-bus) -- DUH Bus Definitions\n* [duh-schema](https://github.com/sifive/duh-schema) -- DUH document JSON schema\n* [duh-core](https://github.com/sifive/duh-core) -- DUH core library\n* [duh-verilog](https://github.com/sifive/duh-verilog) -- Verilog generator from DUH document\n* [duh-svd](https://github.com/sifive/duh-svd) -- DUH to SVD converter\n\n## Example of DUH documents\n\n* [block-ark](https://github.com/sifive/block-ark) for a walk-through\n  example using the DUH suite on a standalone module to produce a valid\n  [duh-document](docs/) that fully describes the mapping of ports to known\n  bus definitions.\n","funding_links":[],"categories":["JavaScript"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsifive%2Fduh","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsifive%2Fduh","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsifive%2Fduh/lists"}