{"id":27038040,"url":"https://github.com/sigma-logic/gowiners","last_synced_at":"2025-04-05T02:19:15.258Z","repository":{"id":271245176,"uuid":"912830052","full_name":"sigma-logic/gowiners","owner":"sigma-logic","description":"Gowin EDA thin oxidized wrapper","archived":false,"fork":false,"pushed_at":"2025-02-04T18:51:08.000Z","size":28,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2025-04-03T04:34:32.911Z","etag":null,"topics":["fpga","hardware","hardware-design","hdl","rust","system-verilog","verilog"],"latest_commit_sha":null,"homepage":"https://crates.io/crates/gowiners","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/sigma-logic.png","metadata":{"files":{"readme":"readme.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-01-06T13:34:19.000Z","updated_at":"2025-02-04T18:51:10.000Z","dependencies_parsed_at":null,"dependency_job_id":"a8c5b1d5-dd2a-4f69-8312-c359cb7ae806","html_url":"https://github.com/sigma-logic/gowiners","commit_stats":null,"previous_names":["sigma-logic/gowiners"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fgowiners","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fgowiners/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fgowiners/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fgowiners/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/sigma-logic","download_url":"https://codeload.github.com/sigma-logic/gowiners/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247276371,"owners_count":20912324,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","hardware","hardware-design","hdl","rust","system-verilog","verilog"],"created_at":"2025-04-05T02:19:14.703Z","updated_at":"2025-04-05T02:19:15.250Z","avatar_url":"https://github.com/sigma-logic.png","language":"Rust","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Gowin EDA wrapper-toolchain\n\n#### 0. Create `.gowin` file contains absolute path to the Gowin EDA installation dir\n```\n/home/limpix/gowin\n```\nand also gitignore it\n\n#### 1. Create `Gowiners.toml` file in root of the project\nand fill it as follows\n```toml\nname = \"key-led\"\nversion = 5\n\n# Device options\n[device]\nfamily = \"GW5AST-138B\"\npart = \"GW5AST-LV138FPG676AC1/I0\"\n\n# Hdl options\n[hdl]\n# Use System Verilog 2017\nstandard = \"sysv2017\"\n# Top module name\ntop = \"top\"\n# Dirs to include\ninclude = [\"include\"]\n\n# Project files\n[files]\ncst = \"phy.cst\"\nverilog = [\n\t\"rtl/top.sv\"\n]\n\n# Place And Route config\n[pnr]\nplace_mode = 0\nroute_mode = 1\nreplicate = false\n\n# Bitstream generation config\n[bitstream]\ncompress = true\n\n# Programmer config\n[programmer]\n# Bitstream file\nfs = \"impl/pnr/project.fs\"\nfrequency = \"2.5Mhz\"\ncable = \"Gowin USB Cable(FT2CH)\"\n\n# SRAM Preset\npreset.sram = { op = \"2\" } # SRAM Program\n# External flash burn preset\npreset.burn = { op = \"53\" } # exFlash Erase,Program 5A\n\n```\n\n#### 2. Run implementation via cli\n```bash\ngowiners impl\n```\nExample output:\n```\nRun implementation\n  Evaluating project\n  Run Gowin EDA syn and pnr tasks\n*** GOWIN Tcl Command Line Console  *** \ncurrent device: GW5AST-138B  GW5AST-LV138FPG676AC1/I0\nadd new file: \"/home/limpix/gowiners/example/phy.cst\"\nadd new file: \"/home/limpix/gowiners/example/rtl/top.sv\"\nGowinSynthesis start\nRunning parser ...\nAnalyzing Verilog file '/home/limpix/gowiners/example/rtl/top.sv'\nCompiling module 'top'(\"/home/limpix/gowiners/example/rtl/top.sv\":1)\nNOTE  (EX0101) : Current top module is \"top\"\n[5%] Running netlist conversion ...\nRunning device independent optimization ...\n[10%] Optimizing Phase 0 completed\n[15%] Optimizing Phase 1 completed\n[25%] Optimizing Phase 2 completed\nRunning inference ...\n[30%] Inferring Phase 0 completed\n[40%] Inferring Phase 1 completed\n[50%] Inferring Phase 2 completed\n[55%] Inferring Phase 3 completed\nRunning technical mapping ...\n[60%] Tech-Mapping Phase 0 completed\n[65%] Tech-Mapping Phase 1 completed\n[75%] Tech-Mapping Phase 2 completed\n[80%] Tech-Mapping Phase 3 completed\n[90%] Tech-Mapping Phase 4 completed\n[95%] Generate netlist file \"/home/limpix/gowiners/example/impl/gwsynthesis/project.vg\" completed\n[100%] Generate report file \"/home/limpix/gowiners/example/impl/gwsynthesis/project_syn.rpt.html\" completed\nGowinSynthesis finish\nReading netlist file: \"/home/limpix/gowiners/example/impl/gwsynthesis/project.vg\"\nParsing netlist file \"/home/limpix/gowiners/example/impl/gwsynthesis/project.vg\" completed\nProcessing netlist completed\nReading constraint file: \"/home/limpix/gowiners/example/phy.cst\"\nPhysical Constraint parsed completed\nRunning placement......\n[10%] Placement Phase 0 completed\n[20%] Placement Phase 1 completed\n[30%] Placement Phase 2 completed\n[50%] Placement Phase 3 completed\nRunning routing......\n[60%] Routing Phase 0 completed\n[70%] Routing Phase 1 completed\n[80%] Routing Phase 2 completed\n[90%] Routing Phase 3 completed\nRunning timing analysis......\n[95%] Timing analysis completed\nPlacement and routing completed\nBitstream generation in progress......\nBitstream generation completed\nRunning power analysis......\n[100%] Power analysis completed\nGenerate file \"/home/limpix/gowiners/example/impl/pnr/project.power.html\" completed\nGenerate file \"/home/limpix/gowiners/example/impl/pnr/project.pin.html\" completed\nGenerate file \"/home/limpix/gowiners/example/impl/pnr/project.rpt.html\" completed\nGenerate file \"/home/limpix/gowiners/example/impl/pnr/project.rpt.txt\" completed\nGenerate file \"/home/limpix/gowiners/example/impl/pnr/project.tr.html\" completed\nMon Jan  6 14:14:16 2025\n\nCompleted\n```\n\n#### 3. Flash bitstream\nDrive your design in real life\n```bash\n# Where `sram` is programmer preset defined earlier in Gowiners.toml\ngowiners flash sram\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsigma-logic%2Fgowiners","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsigma-logic%2Fgowiners","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsigma-logic%2Fgowiners/lists"}