{"id":28333684,"url":"https://github.com/sigma-logic/hvtx","last_synced_at":"2026-01-28T15:31:17.179Z","repository":{"id":275180273,"uuid":"921373217","full_name":"sigma-logic/hvtx","owner":"sigma-logic","description":"HDMI Transmitter(Source) Core for Arora FPGA family","archived":false,"fork":false,"pushed_at":"2025-07-29T20:29:05.000Z","size":131,"stargazers_count":3,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-07-29T22:59:41.399Z","etag":null,"topics":["dvi","fpga","gowin","hardware","hardware-design","hdl","hdmi","verilog"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/sigma-logic.png","metadata":{"files":{"readme":"readme.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2025-01-23T20:39:59.000Z","updated_at":"2025-07-29T20:29:09.000Z","dependencies_parsed_at":null,"dependency_job_id":"70c293c4-01cb-4f3f-aa35-4e11b89746ad","html_url":"https://github.com/sigma-logic/hvtx","commit_stats":null,"previous_names":["sigma-logic/hdmi-14-tx"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/sigma-logic/hvtx","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fhvtx","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fhvtx/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fhvtx/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fhvtx/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/sigma-logic","download_url":"https://codeload.github.com/sigma-logic/hvtx/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sigma-logic%2Fhvtx/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28846340,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-28T15:15:36.453Z","status":"ssl_error","status_checked_at":"2026-01-28T15:15:13.020Z","response_time":57,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["dvi","fpga","gowin","hardware","hardware-design","hdl","hdmi","verilog"],"created_at":"2025-05-26T20:51:59.741Z","updated_at":"2026-01-28T15:31:17.174Z","avatar_url":"https://github.com/sigma-logic.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Hdmi Video Transmitter (HVTX)\n\n### Features\n* For **Arora** FPGA family\n* **Compact** - not exceed **200** LUTs, **200** FFs\n* **Modular** - Divided into convenient modules\n* **Fmax** - \u003e 165 Mhz\n\n### Notes\n* **Video Only** - only for clean video output\n* **RGB888** - the only format supported, but theoretically can do more as it modular\n* **DVI** - doesn't use preamble and guard intervals to stay simple\n\n### In The Future\n* **AXI** streaming support\n\n## Modules and usage\nCopy the core [file](https://github.com/sigma-logic/hvtx/tree/main/src/hvtx.sv) to your project\n\nComplete example can be found [here](https://github.com/sigma-logic/hvtx/tree/main/src/top.sv)\n\n#### `hvtx_cursor`\nSlides the cursor over a frame of the specified size\n```sv\nhvtx_cursor #\n( .WID(WIDTH)\n, .FRAME_WIDTH(1650)\n, .FRAME_HEIGHT(750)\n) u_cursor\n( .i_clk(pixel_clk)\n, .i_rst(~rst_n)\n, .o_x(x)\n, .o_y(y)\n);\n```\n\n#### `hvtx_sync`\nGenerates synchronization pulses based on the cursor position in the frame.\\\nLatency: 2\n```sv\nhvtx_sync #\n( .WID(WIDTH)\n, .FRAME_WIDTH(1650)\n, .FRAME_HEIGHT(750)\n, .ACTIVE_WIDTH(1280)\n, .ACTIVE_HEIGHT(720)\n, .H_PORCH(110)\n, .H_SYNC(40)\n, .V_PORCH(5)\n, .V_SYNC(5)\n) u_sync\n( .i_clk(pixel_clk)\n, .i_x(x)\n, .i_y(y)\n, .o_hs(hs) // H Sync\n, .o_vs(vs) // V Sync\n, .o_de(de) // Active video\n);\n```\n\n#### `hvtx_mod`\nCombines current timings and active video data and produces a vector of 3 modulated tmds 10-bit symbols (per channel) ready for transmission\\\nLatency: 4\n```sv\nhvtx_mod u_mod\n( .i_pclk(pixel_clk)\n, .i_sclk(serial_clk)\n, .i_rst(~rst_n)\n, .i_hs(hs)\n, .i_vs(vs)\n, .i_de(de)\n, .i_video(video)\n, .o_chan_vec(chan_vec)\n);\n```\n\n#### `hvtx_ser`\nSerializes tmds symbols and passes them to the LVDS output buffer. Serial clock should be **5** times faster than pixel clock. It is recommended to synthesize fast clock and then divide it by 5 to get pixel clock.\n```sv\nhvtx_ser u_ser\n( .i_pclk(pixel_clk)\n, .i_sclk(serial_clk)\n, .i_rst(~rst_n)\n, .i_chan_vec(chan_vec)\n, .o_hdmi_clk_p(hdmi_clk_p_a)\n, .o_hdmi_clk_n(hdmi_clk_n_a)\n, .o_hdmi_chan_p(hdmi_chan_p_a)\n, .o_hdmi_chan_n(hdmi_chan_n_a)\n);\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsigma-logic%2Fhvtx","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsigma-logic%2Fhvtx","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsigma-logic%2Fhvtx/lists"}