{"id":37607506,"url":"https://github.com/siliconcompiler/fpga-timing-coverage-suite","last_synced_at":"2026-01-16T10:13:39.947Z","repository":{"id":320302111,"uuid":"1081587108","full_name":"siliconcompiler/fpga-timing-coverage-suite","owner":"siliconcompiler","description":null,"archived":false,"fork":false,"pushed_at":"2025-12-02T20:19:10.000Z","size":21018,"stargazers_count":3,"open_issues_count":0,"forks_count":1,"subscribers_count":0,"default_branch":"master","last_synced_at":"2025-12-05T20:28:05.696Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/siliconcompiler.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2025-10-23T01:56:28.000Z","updated_at":"2025-12-02T20:19:16.000Z","dependencies_parsed_at":"2025-10-23T03:38:29.366Z","dependency_job_id":"67d3f905-07b1-4857-a99a-47620241a64e","html_url":"https://github.com/siliconcompiler/fpga-timing-coverage-suite","commit_stats":null,"previous_names":["alexandresinger/fpga-timing-benchmarks","siliconcompiler/fpga-timing-coverage-suite"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/siliconcompiler/fpga-timing-coverage-suite","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Ffpga-timing-coverage-suite","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Ffpga-timing-coverage-suite/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Ffpga-timing-coverage-suite/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Ffpga-timing-coverage-suite/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/siliconcompiler","download_url":"https://codeload.github.com/siliconcompiler/fpga-timing-coverage-suite/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Ffpga-timing-coverage-suite/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28478049,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-16T06:30:42.265Z","status":"ssl_error","status_checked_at":"2026-01-16T06:30:16.248Z","response_time":107,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2026-01-16T10:13:39.877Z","updated_at":"2026-01-16T10:13:39.938Z","avatar_url":"https://github.com/siliconcompiler.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# FPGA Timing Benchmarks\n\nThis is an open source collection of timing constraint files targeted towards\nqualifying the timing capabilities of an FPGA CAD flow, such as VTR.\nProvided is also a set of scripts which can run these benchmarks on VPR, targeting\nZero ASIC's z1010 architecture; however, this can be used to target any VTR-compatible\narchitecture.\n\n![fpga-timing-benchmark-flow.png](./docs/images/fpga-timing-benchmark-flow.png)\n\n## Getting Started\n\n### Tools Installation\n\nThe scripts require some CAD tools in order to run and test the benchmarks. We\nwill be using the SiliconCompiler project to manage the tools and versions.\nThe following commands should install the correct versions of the tools that this\nproject requires..\n```\n# Optional: Create a python virtual environment.\npython3 -m venv .venv\nsource .venv/bin/activate\n\n# Install this directory as a Python module.\npip install .\n\n# Install siliconcompiler.\npip install --upgrade siliconcompiler\n\n# Install necessary tools using SiliconCompiler (these should update your PATH).\nsc-install yosys-wildebeest opensta vpr\n```\n\n### Architecture Download\n\nFor the tests in this benchmark, we will run them on Zero ASIC's z1010 architecture.\nThe choice of architecture was somewhat arbitrary; however, we do need an architecture\nthat has the necessary liberty files which can be used for post-implementation\ntiming analysis. This architecture is also built-into Wildebeest right now,\nso it is slightly more convenient.\nThe following commands will download the latest release of the z1010 architecture\nand untar it into this directory.\n```\nwget https://github.com/siliconcompiler/logiklib/releases/download/v0.2.0/z1010_cad.tar.gz\ntar -xvzf z1010_cad.tar.gz\n```\n\n### Running the Benchmarks\n\n```py\n# Run the benchmarks through the test suite.\npython3 run_suite.py\n\n# The results are returned as a CSV file in a run directory.\n# Optional: These results can be visualized using the following script:\npip install .[vis_scripts]\npython3 scripts/visualize_results.py --input runs/run001/results.csv --output runs/run001/results.png\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsiliconcompiler%2Ffpga-timing-coverage-suite","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsiliconcompiler%2Ffpga-timing-coverage-suite","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsiliconcompiler%2Ffpga-timing-coverage-suite/lists"}