{"id":13774189,"url":"https://github.com/siliconcompiler/logik","last_synced_at":"2026-01-14T06:58:55.426Z","repository":{"id":231166524,"uuid":"738710442","full_name":"siliconcompiler/logik","owner":"siliconcompiler","description":"A configurable RTL to bitstream FPGA toolchain","archived":false,"fork":false,"pushed_at":"2025-12-15T23:45:05.000Z","size":10181,"stargazers_count":55,"open_issues_count":2,"forks_count":5,"subscribers_count":4,"default_branch":"main","last_synced_at":"2025-12-19T08:17:17.904Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"https://logik.readthedocs.io/en/latest/","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/siliconcompiler.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2024-01-03T21:37:13.000Z","updated_at":"2025-12-15T23:45:07.000Z","dependencies_parsed_at":"2024-04-17T08:44:15.065Z","dependency_job_id":"03f312f5-fb12-44eb-813d-dbca4e565f36","html_url":"https://github.com/siliconcompiler/logik","commit_stats":null,"previous_names":["zeroasiccorp/logik","siliconcompiler/logik"],"tags_count":9,"template":false,"template_full_name":null,"purl":"pkg:github/siliconcompiler/logik","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Flogik","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Flogik/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Flogik/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Flogik/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/siliconcompiler","download_url":"https://codeload.github.com/siliconcompiler/logik/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/siliconcompiler%2Flogik/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28412478,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-14T05:26:33.345Z","status":"ssl_error","status_checked_at":"2026-01-14T05:21:57.251Z","response_time":107,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-03T17:01:24.492Z","updated_at":"2026-01-14T06:58:55.420Z","avatar_url":"https://github.com/siliconcompiler.png","language":"Python","funding_links":[],"categories":["FPGA Design","Python"],"sub_categories":[],"readme":"Logik\n-------------------------------------------------------------\n\n[![Regression](https://github.com/siliconcompiler/logik/actions/workflows/regression.yml/badge.svg)](https://github.com/siliconcompiler/logik/actions/workflows/regression.yml)\n[![Lint](https://github.com/siliconcompiler/logik/actions/workflows/lint.yml/badge.svg)](https://github.com/siliconcompiler/logik/actions/workflows/lint.yml)\n[![License](https://img.shields.io/badge/License-Apache_2.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)\n\nLogik is an open source FPGA tool chain with support for high level language parsing, synthesis, placement, routing, bit-stream generation, and analysis. Users enter design sources, constraints, and compile options through a simple [SiliconCompiler](https://github.com/siliconcompiler/siliconcompiler/) Python API. Once setup is complete, automated compilation can be initiated with a single line run command. Logik relies on the [Logiklib](https://github.com/siliconcompiler/logiklib) project for all architecture and device descriptions.\n\n![logik_flow](images/logik-plus-open-sta-flow.png)\n\nLogik supports most of the features you would expect in a commercial proprietary FPGA tool chain.\n\n| Feature                  | Status |\n|--------------------------|--------|\n| Design languages         | SystemVerilog, Verilog, VHDL\n| DSP synthesis            | Supported\n| RAM synthesis            | Supported\n| Timing constraints (SDC) | Supported\n| Pin Constraints (PCF)    | Supported\n| Bitstream generation     | Supported\n| IP management            | Supported\n| Remote compilation       | Supported\n| Multi-clock designs      | Supported\n| Supported devices        | Logiklib devices\n\n## Getting Started\n\nThe Logik tool chain is available through PyPi and can be installed using pip.\n\n```sh\npython -m pip install --upgrade logik\n```\n\nAll open source FPGA pre-requisites can be installed via the SiliconCompiler `sc-install` utility.\n\n```sh\nsc-install -group fpga opensta\n```\n\nThe following example illustrate some essential Logik features. For complete documentation of all options available, see the [SiliconCompiler project](https://github.com/siliconcompiler/siliconcompiler/blob/main/README.md).\n\n```python\n\nimport siliconcompiler\nfrom logik.flows.logik_flow import LogikFlow\nfrom logiklib.zeroasic.z1000 import z1000\n\n# 1. Create a Design object to hold source files and constraints.\ndesign = siliconcompiler.Design('adder')\ndesign.add_file('adder.v', fileset=\"rtl\")\ndesign.set_topmodule('adder', fileset=\"rtl\")\n\n# 2. Create an FPGA project\nproject = siliconcompiler.FPGA(design)\n\n# 3. Assign file sets to use for elaboration\nproject.add_fileset('rtl')\n\n# 4. Select the rtl2bits flow to use\nproject.set_flow(LogikFlow())\n\n# 5. Load FPGA part settings and associated flow and libraries.\nproject.set_fpga(z1000.z1000())\n\n# 6. User defined options\nproject.option.set_quiet(True)\n\n# 7. Run compilatin\nproject.run()\n\n#6. Display summary of results\nproject.summary()\n\n```\n\n\u003e [!NOTE]\n\u003e The required files can be found at: [heartbeat example](https://github.com/siliconcompiler/logik/tree/main/examples/adder)\n\n## Examples\n\n* [Ethernet](./examples/eth_mac_1g/eth_mac_1g.py): Ethernet MAC compiled for the `z1000` architecture\n* [Adder](examples/adder/adder.py): Small adder example compiled for the `z1000` architecture.\n* [Picorv32](examples/picorv32/picorv32.py): picorv32 RISC-V CPU example compiled for the `z1062` architecture.\n\n## Documentation\n\n* [Logik Documentation](https://logik.readthedocs.io/en/latest/)\n* [SiliconCompiler Documentation](https://docs.siliconcompiler.com/en/stable/)\n\n\n## Installation\n\nLogik is available as wheel packages on PyPI for macOS, Windows and Linux platforms. For a Python 3.8-3.12 environment, just use pip to install.\n\n```sh\npython -m pip install --upgrade logik\n```\n\nRunning natively on your local machine will require installing a number of prerequisites:\n\n* [Silicon Compiler](https://github.com/siliconcompiler/siliconcompiler): Hardware compiler framework\n* [Slang](https://github.com/MikePopoloski/slang): SystemVerilog Parser\n* [GHDL](https://ghdl.github.io/ghdl/): VHDL parser\n* [Yosys](https://github.com/YosysHQ/yosys): Logic synthesis platform\n* [Wildebeest](https://github.com/zeroasiccorp/wildebeest): High performance synthesis yosys plugin\n* [VPR](https://github.com/verilog-to-routing/vtr-verilog-to-routing): FPGA place and route\n* [FASM](https://github.com/chipsalliance/fasm): FPGA assembly parser and generator\n* [OpenSTA](https://github.com/The-OpenROAD-Project/OpenSTA): Production grade static timing analysis engine\n\nWe recommend using the SiliconCompiler `sc-install` utility to automatically install the correct versions of all open source FPGA tool dependencies.\n\n```sh\nsc-install -group fpga opensta\n```\n\nDetailed installation instructions can be found in the [SiliconCompiler Installation Guide](https://docs.siliconcompiler.com/en/stable/user_guide/installation.html#external-tools).\n\n\n## License\n\nThe Logik project is licensed under the open source [Apache License 2.0](LICENSE). For licensing terms of all dependencies, visit depedency repository.\n\n## Issues / Bugs\nWe use [GitHub Issues](https://github.com/siliconcompiler/logik/issues) for tracking requests and bugs.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsiliconcompiler%2Flogik","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsiliconcompiler%2Flogik","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsiliconcompiler%2Flogik/lists"}