{"id":20746191,"url":"https://github.com/sinakarvandi/fpga","last_synced_at":"2026-03-19T17:19:59.735Z","repository":{"id":62314684,"uuid":"254872201","full_name":"SinaKarvandi/FPGA","owner":"SinaKarvandi","description":"Random FPGA Projects","archived":false,"fork":false,"pushed_at":"2023-04-24T05:54:44.000Z","size":7903,"stargazers_count":2,"open_issues_count":0,"forks_count":1,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-01-18T02:44:40.594Z","etag":null,"topics":["chisel3","fpga","verilog","vhdl","vitis","vivado","zynq"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/SinaKarvandi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-04-11T13:20:39.000Z","updated_at":"2024-11-12T19:49:02.000Z","dependencies_parsed_at":"2023-01-30T05:30:55.112Z","dependency_job_id":null,"html_url":"https://github.com/SinaKarvandi/FPGA","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2FFPGA","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2FFPGA/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2FFPGA/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2FFPGA/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/SinaKarvandi","download_url":"https://codeload.github.com/SinaKarvandi/FPGA/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243040712,"owners_count":20226334,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel3","fpga","verilog","vhdl","vitis","vivado","zynq"],"created_at":"2024-11-17T07:25:58.641Z","updated_at":"2025-12-24T11:51:27.805Z","avatar_url":"https://github.com/SinaKarvandi.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# FPGA Projects\n\nThis repo contains a collection of my fun FPGA projects. All of them are based on Xilinx FPGAs, Spartan6 (ISE Design Suite), and Zynq (ZedBoard, Pynq z1 - Vivado and Vitis IDE).\n\n## Zynq\n\nThe following projects are in this directory `VGA Interface`, `VGA Snake Game`, `Block Ram Reset`, `Chisel Tests`, `Zedboard OLED Interface`, SPI Controller`.\n\n### VGA Interface\nHere's the pictures of VGA interface, written in VHDL.\n\nVGA Interface 1 |   VGA Interface 2            \n:-------------------------:|:-------------------------:\n![](https://raw.githubusercontent.com/SinaKarvandi/FPGA/master/img/VGA-interface1.jpg)  |  ![](https://raw.githubusercontent.com/SinaKarvandi/FPGA/master/img/VGA-interface2.jpg) \n\n### VGA Snake Game\n\nHere's the pictures of SNAKE game, written in VHDL.\n  1 |      2        |      3        |       4       \n:-------------------------:|:-------------------------:|:-------------------------:|:-------------------------:\n![](https://raw.githubusercontent.com/SinaKarvandi/FPGA/master/img/Snake1.jpg)     |  ![](https://raw.githubusercontent.com/SinaKarvandi/FPGA/master/img/Snake2.jpg) | ![](https://raw.githubusercontent.com/SinaKarvandi/FPGA/master/img/Snake3.jpg)   | ![](https://raw.githubusercontent.com/SinaKarvandi/FPGA/master/img/Snake4.jpg)\n\n\n\n## Spartan6\n\nThe following projects are in this directory `ClkDivider`, `Debouncer`, `PWM`, `PatternRecognitionBitStream`, `PriorityEncoder`, `TriStateBuffer`.\n\n\n## License\nAll of these projects are licensed under MIT LICENSE.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsinakarvandi%2Ffpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsinakarvandi%2Ffpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsinakarvandi%2Ffpga/lists"}