{"id":20746185,"url":"https://github.com/sinakarvandi/hardware-design-stack","last_synced_at":"2026-02-25T06:04:03.422Z","repository":{"id":198239959,"uuid":"700364374","full_name":"SinaKarvandi/hardware-design-stack","owner":"SinaKarvandi","description":"The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/","archived":false,"fork":false,"pushed_at":"2023-10-08T09:16:47.000Z","size":48,"stargazers_count":8,"open_issues_count":0,"forks_count":2,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-11T13:26:17.365Z","etag":null,"topics":["asic","asic-design","chisel","chisel3","fpga","gtkwave","modelsim","netlist","openlane","openram","verilator","verilog","vhdl","vitis","vitis-hls","vivado","vivado-hls"],"latest_commit_sha":null,"homepage":"https://rayanfam.com/topics/hardware-design-stack/","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/SinaKarvandi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-10-04T13:10:10.000Z","updated_at":"2024-11-09T20:43:38.000Z","dependencies_parsed_at":"2023-10-05T00:57:44.018Z","dependency_job_id":"b9010b1a-961a-4e10-99e4-7ace0f14abac","html_url":"https://github.com/SinaKarvandi/hardware-design-stack","commit_stats":null,"previous_names":["sinakarvandi/hardware-design-stack"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/SinaKarvandi/hardware-design-stack","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2Fhardware-design-stack","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2Fhardware-design-stack/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2Fhardware-design-stack/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2Fhardware-design-stack/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/SinaKarvandi","download_url":"https://codeload.github.com/SinaKarvandi/hardware-design-stack/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SinaKarvandi%2Fhardware-design-stack/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":281139043,"owners_count":26450141,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-26T02:00:06.575Z","response_time":61,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","asic-design","chisel","chisel3","fpga","gtkwave","modelsim","netlist","openlane","openram","verilator","verilog","vhdl","vitis","vitis-hls","vivado","vivado-hls"],"created_at":"2024-11-17T07:25:57.638Z","updated_at":"2025-10-26T17:04:43.686Z","avatar_url":"https://github.com/SinaKarvandi.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Hardware Design Stack\n\nWelcome to the repository for the source codes discussed in the blog post available at [https://rayanfam.com/topics/hardware-design-stack](https://rayanfam.com/topics/hardware-design-stack/).\n\n## Description\n\nAre you interested in delving into the fascinating world of hardware design? This repository is your gateway to exploring the intricacies of hardware design, from understanding fundamental concepts to hands-on experience with hardware description languages, synthesis, simulation, and more. In the blog post associated with this repository, we take you on a journey through the hardware design landscape, offering insights into various aspects, tools, and techniques that are crucial for designing and implementing hardware systems.\n\n## Table of Contents\n\n- Introduction\n- Analog Signals/Protocols\n- Digital Signals/Protocols\n- Source Code\n- Moore’s Law \u0026 Amdahl’s Law\n- Terms\n- Hardware Description Languages\n- Generating Hardware Using Chisel\n- C/C++ in Hardware Design\n- Vitis HLS\n- Simulating Codes\n- Simulating HDL Code Using GTKWave or ModelSim\n- Testing Codes in Chisel\n- Testing HDL Codes Using Verilator\n- Synthesising HDL Codes\n- Programming Xilinx FPGAs Using Vivado\n- Vivado Netlists\n- The Memory\n- Distributed RAMs in FPGAs\n- Block RAM (BRAM) in FPGAs\n- Static RAM (SRAM) in ASIC\n- Elaborating ASIC Designs\n- Building Hardware Layout (GDSII)\n- Reverse Engineering Netlists\n- Conclusion\n- References\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsinakarvandi%2Fhardware-design-stack","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsinakarvandi%2Fhardware-design-stack","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsinakarvandi%2Fhardware-design-stack/lists"}