{"id":23296724,"url":"https://github.com/skpro-glitch/parallel_multiplier","last_synced_at":"2026-03-20T01:08:07.046Z","repository":{"id":267921838,"uuid":"902761875","full_name":"SKpro-glitch/Parallel_Multiplier","owner":"SKpro-glitch","description":"Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado. ","archived":false,"fork":false,"pushed_at":"2025-06-19T03:52:13.000Z","size":57,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2026-01-22T03:40:50.679Z","etag":null,"topics":["asic","asic-design","fpga","fpga-programming","multiplier","parallel-multiplication","register-transfer-level","rtl","rtl-design","systemverilog","systemverilog-test-bench","verilog-hdl","vlsi-design","xilinx-vivado"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/SKpro-glitch.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2024-12-13T08:07:36.000Z","updated_at":"2025-06-19T03:52:16.000Z","dependencies_parsed_at":"2024-12-13T09:33:38.637Z","dependency_job_id":null,"html_url":"https://github.com/SKpro-glitch/Parallel_Multiplier","commit_stats":null,"previous_names":["skpro-glitch/parallel_multiplier"],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/SKpro-glitch/Parallel_Multiplier","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SKpro-glitch%2FParallel_Multiplier","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SKpro-glitch%2FParallel_Multiplier/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SKpro-glitch%2FParallel_Multiplier/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SKpro-glitch%2FParallel_Multiplier/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/SKpro-glitch","download_url":"https://codeload.github.com/SKpro-glitch/Parallel_Multiplier/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SKpro-glitch%2FParallel_Multiplier/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28942291,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-31T11:39:38.044Z","status":"ssl_error","status_checked_at":"2026-01-31T11:39:27.765Z","response_time":128,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","asic-design","fpga","fpga-programming","multiplier","parallel-multiplication","register-transfer-level","rtl","rtl-design","systemverilog","systemverilog-test-bench","verilog-hdl","vlsi-design","xilinx-vivado"],"created_at":"2024-12-20T07:13:42.298Z","updated_at":"2026-03-20T01:08:07.025Z","avatar_url":"https://github.com/SKpro-glitch.png","language":"SystemVerilog","readme":"# Parameteirzed Parallel Multiplier\n\n**Generic, Parameterized RTL for High-Speed Arithmetic**\n\n## 1. Overview\n\nThis IP is a high-speed Parallel Multiplier. This module utilizes a Carry Save Adder for fast computation of partial prducts, making it ideal for high-frequency DSP applications, Cryptography, and ALU design.\n\n## 2. Key Features\n\n* **Linear Delay:** Path delay of an Array multiplier is proportional to O(N), where N is the bit width.\n\n* **Fully Parameterized:** Easily configure bit widths (e.g., 8x8, 16x16, 32x32) via Verilog parameters.\n\n* **Combinational Choice:** Can be used as a fully combinational module (Multiplier) or as a synchronous module with registers (Multiplier_Wrapper) with no change in functionality.\n\n* **FPGA Ready:** Optimized for synthesis on Xilinx Vivado.\n\n* **Verification:** Includes a self-checking testbench with random stimulus (constrained-random).\n\n## 3. Project Structure\n\n**Root Directory**\n\n* `LICENSE`: Apache 2.0 License.\n\n* `README.md`: This file.\n\n`/rtl` - **Design Under Test**\n\n* `Multiplier.sv`: The main SystemVerilog RTL source for the multiplier. Can be instantiated without the Wrapper for fully combinational use.\n\n* `Multiplier_Wrapper.sv`: The register wrapper for the Multiplier. Without this, static timing analysis cannot be done.\n\n* `Inter_Prod.sv`: Intermediate module to implement the Carry Save Adder. Fully combinational, but cannot be used independently.\n\n`/sim` - **Verification Environment**\n\n* `multiplier_uvm_pkg.sv`: The UVM package (includes all classes).\n\n* `interface.sv`: SystemVerilog interface for DUT connection.\n\n* `tb_top.sv`: Hardware top module for simulation.\n\n* `Makefile.vivado`: Automation for AMD Vivado (XSIM).\n\n* `Makefile.questa`: Automation for Siemens Questa/ModelSim.\n\n* `README_DEV.md`: Developer guide for running simulations.\n\n* Other tb files are also present here. Refer to `README_DEV.md` for more information.\n\n`/syn` - **Synthesis \u0026 Benchmarking**\n\n* `syn_vivado.tcl`: Non-project mode Vivado synthesis script.\n\n* `timing.xdc`: Timing constraints.\n\n## 4. Technical Specifications (Data Sheet)\n\n|  Width |  Logic Cells (LUTs)   |  Critical Path (ns)   |  Max Freq (MHz) |\n|  :---: |  :---: |  :---: |  :---: |\n|  8x8   |  ~70   |  5.362 ns   |  186.498 MHz   |\n|  16x16 |  ~360  |  10.865 ns   |  92.039 MHz   |\n|  32x32 |  ~1920 |  18.489 ns   |  54.086 MHz   |\n\n* Latency with Wrapper = 1 cycle\n* Latency without Wrapper = 0 cycles (Fully Combinational)\n\n**Note:** Performance data based on *Xilinx Zynq-7000 xc7z012sclg485-2* synthesis.\n\n## 5. Architecture Detail\n\nThe design implements the following reductions:\n\n* **Carry Save Adder:** A Carry Save Adder which reduce the size of the critical path to enhance the speed.\n\n* **Intermediate Product:** Each stage of the Carry Save Adder produces an Intermediate Product.\n\n## 6. View Port Descriptions\n\n|   Port Name   |   Direction   |   Width   |   Description   |\n|   :---:   |   :---:   |   :---:   |   :--- |\n|   a   |   Input   |   [N-1:0]   |   Multiplicand   |\n|   b   |   Input   |\t[N-1:0]   |   Multiplier   |\n|   p   |\tOutput   |\t[2N-1:0]   |   Final Product (A×B)   |\n\n## 7. Quick Start\n\n**Simulate on Linux CLI (Vivado):**\n```bash\ncd \u003cpath to folder\u003e/sim\nmake -f Makefile.vivado N=32\n```\n**Simulate on Windows (Vivado)**\n1. Ensure **Vivado** is in your System PATH.\n2. Install **make** (via [GNUWin32](https://gnuwin32.sourceforge.net/packages/make.htm)).\n3. Open Command Prompt in the `sim/` directory.\n4. Open and uncomment the respective commands for Windows in the `Makefile.vivado`\n5. Run the simulation:\n```bash\nmake -f Makefile.vivado N=32\n```\n**Synthesize (Vivado):**\n```bash\ncd \u003cpath to folder\u003e/syn\nvivado -mode batch -source syn_vivado.tcl -tclargs 32 20.0\n```\n\\* TCL Arguments: Bit Width (N) = 32, Clock Period (PERIOD) = 20.0\n\n*Note:* Simulation and Synthesis scripts are provided only for AMD Vivado. For Intel Quartus or other platforms, the RTL is standard SystemVerilog and can be imported directly into any standard flow.\n\n## 8. Usage Example (Instantiation)\n\n**With Wrapper:**\n```bash\n   Multiplier_Wrapper #(.N(32)) mul (\n        .clk(clk),\n        .rst(reset),\n        .a_in(input_a),\n        .b_in(input_b),\n        .p(result)\n   );\n```\n\n**Without Wrapper:**\n```bash\n   Multiplier #(.N(32)) mul (\n        .a(input_a),\n        .b(input_b),\n        .p(result)\n   );\n```\n\n## 9. Sample Schematic\n\n**Multiplier Schematic:** 4x4 multiplier\n\u003cbr\u003e\n![image](https://github.com/user-attachments/assets/b64028a8-f875-4ddb-a9af-f5702b26bf18)\n\u003cbr\u003e\n\n**Adder Row Schematic:** Individual instance of Intermediate Product module for 4-bit width\n\u003cbr\u003e\n![image](https://github.com/user-attachments/assets/71dfe993-168c-44d8-8bf0-0bca8460cf78)\n\n\n## 10. License\n\nLicensed under the Apache License, Version 2.0. You may use this IP in both open-source and commercial projects. See the [Apache 2.0 License](LICENSE) file for details.\n\n## 11. Contact\n\n**Email:** sohamkapur134@gmail.com\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fskpro-glitch%2Fparallel_multiplier","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fskpro-glitch%2Fparallel_multiplier","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fskpro-glitch%2Fparallel_multiplier/lists"}