{"id":13465861,"url":"https://github.com/skyzh/RISCV-Simulator","last_synced_at":"2025-03-25T21:30:35.582Z","repository":{"id":38347701,"uuid":"194653853","full_name":"skyzh/RISCV-Simulator","owner":"skyzh","description":"💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. 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Support RV32I ISA.\n\nGenerally this should be done with a **5-stage pipeline**. This implementation may be found at [pipeline](https://github.com/skyzh/RISCV-Simulator/tree/pipeline) branch.\n\nAll CPU and CPU simulators I've made are listed below.\n\n|                                                                     | Technique                                      | Implementation |\n|---------------------------------------------------------------------|------------------------------------------------|----------------|\n| [RISC-V v1](https://github.com/skyzh/RISCV-Simulator/tree/pipeline) | 5-stage pipeline  simulator                 | C++            |\n| [RISC-V v2](https://github.com/skyzh/RISCV-Simulator)               | dynamic scheduling simulator \u003cbr\u003e Tomasulo + Speculation | C++            |\n| [MIPS](https://github.com/skyzh/mips-simulator)                     | 5-stage pipeline  simulator                             | Haskell        |\n| [MIPS](https://github.com/skyzh/mips-cpu)                           | 5-stage pipeline CPU        | Verilog        |\n\nThe architecture is derived from **Tomasulo** and **Speculation** described in CA:AQA Chapter 3. While the method in the textbook is not detailed enough to carry out a CPU design (It illustrates the algorithm with only one float unit instead of a CPU), I came up with some ideas to complete the design for a fully-functional RISC-V CPU. It can be summarized as follows:\n\n* Handle memory hazards\n* RISC-V `jalr` instruction\n* Handle branch mis-prediction in the architecture with just Tomasulo algorithm\n\nFor a full report on how I made this simulator and solutions to the challenges above, refer to [Make You a RISC-V Simulator (PDF, Chinese)](https://github.com/skyzh/RISCV-Simulator/files/3389385/make-you-a-riscv-simulator.final.2.pdf)\n\nFor statistics and reports on sample programs, refer to [Travis-CI build log](https://travis-ci.com/github/skyzh/RISCV-Simulator).\n\nThis branch simulates a RISC-V CPU of 2 stage: issue and execute, \nwhich supports out-of-order execution.\n\nIt implements out-of-order execution with Tomasulo algorithm. \nFor branch, It applies hardware speculation to speculate the following\ninstructions. 3 load buffer, 3 store buffer, 4 ALU unit, and a 12-entry \nreorder buffer. Use Two-level adaptive predictor for branch prediction.\n\nNote that since I was unable to design the equivalent circuit, this branch \njust shows a programmer's way to illustrate out-of-order execution design.\n\nYou may go into Presentation Mode to view detailed execution information.\n\n\u003cimg width=\"1680\" alt=\"Screen Shot 2019-09-06 at 10 07 22 AM\" src=\"https://user-images.githubusercontent.com/4198311/64395894-5dd9d080-d08e-11e9-8b7c-888b3018f431.png\"\u003e\n\n\n| Branch        |  Build Status | Note |\n| ------------- | ------------- | ------------- |\n| [seq](https://github.com/skyzh/RISCV-Simulator/tree/seq)  | [![Build Status](https://travis-ci.com/skyzh/RISCV-Simulator.svg?branch=seq)](https://travis-ci.com/skyzh/RISCV-Simulator)  | A sequential implementation. First edition. No feed forward. |\n| [feedforward](https://github.com/skyzh/RISCV-Simulator/tree/feedforward)  | [![Build Status](https://travis-ci.com/skyzh/RISCV-Simulator.svg?branch=feedforward)](https://travis-ci.com/skyzh/RISCV-Simulator)  | Second edition. Based on seq. Feeding forward runs faster. (Though I don't like it.) |\n| [pipeline](https://github.com/skyzh/RISCV-Simulator/tree/pipeline)  | [![Build Status](https://travis-ci.com/skyzh/RISCV-Simulator.svg?branch=pipeline)](https://travis-ci.com/skyzh/RISCV-Simulator)  | Pipelined version. Based on seq. Handle hazard by forwarding. Two-level adaptive predictor. |\n| [out-of-order](https://github.com/skyzh/RISCV-Simulator/tree/out-of-order)  | [![Build Status](https://travis-ci.com/skyzh/RISCV-Simulator.svg?branch=out-of-order)](https://travis-ci.com/skyzh/RISCV-Simulator)  | Out-of-order execution with Tomasulo algorithm and Speculation. |\n| [master](https://github.com/skyzh/RISCV-Simulator/tree/master)  | [![Build Status](https://travis-ci.com/skyzh/RISCV-Simulator.svg?branch=master)](https://travis-ci.com/skyzh/RISCV-Simulator)  | For online judge |\n","funding_links":[],"categories":["C++","资源清单"],"sub_categories":["CS1956 (原 MS125) - 编程综合实践 (荣誉)"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fskyzh%2FRISCV-Simulator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fskyzh%2FRISCV-Simulator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fskyzh%2FRISCV-Simulator/lists"}