{"id":13537437,"url":"https://github.com/sld-columbia/esp","last_synced_at":"2026-04-02T00:28:46.677Z","repository":{"id":37795963,"uuid":"190284572","full_name":"sld-columbia/esp","owner":"sld-columbia","description":"Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy","archived":false,"fork":false,"pushed_at":"2026-03-16T05:06:35.000Z","size":277147,"stargazers_count":405,"open_issues_count":42,"forks_count":137,"subscribers_count":26,"default_branch":"main","last_synced_at":"2026-03-16T14:49:07.886Z","etag":null,"topics":["accelerators","asic","embedded-systems","fpga","network-on-chip","riscv","system-on-chip"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/sld-columbia.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2019-06-04T21:53:02.000Z","updated_at":"2026-03-12T20:13:37.000Z","dependencies_parsed_at":"2023-02-14T12:16:10.068Z","dependency_job_id":"2e0330fd-e524-41b9-baad-6cd79fc7bb3b","html_url":"https://github.com/sld-columbia/esp","commit_stats":null,"previous_names":[],"tags_count":9,"template":false,"template_full_name":null,"purl":"pkg:github/sld-columbia/esp","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sld-columbia%2Fesp","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sld-columbia%2Fesp/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sld-columbia%2Fesp/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sld-columbia%2Fesp/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/sld-columbia","download_url":"https://codeload.github.com/sld-columbia/esp/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sld-columbia%2Fesp/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":31293376,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-01T21:15:39.731Z","status":"ssl_error","status_checked_at":"2026-04-01T21:15:34.046Z","response_time":53,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["accelerators","asic","embedded-systems","fpga","network-on-chip","riscv","system-on-chip"],"created_at":"2024-08-01T09:00:59.095Z","updated_at":"2026-04-02T00:28:46.669Z","avatar_url":"https://github.com/sld-columbia.png","language":"C","funding_links":[],"categories":["Systems"],"sub_categories":[],"readme":"![Open-ESP](esp-logo-small.png)\n\n[![DOI](https://zenodo.org/badge/190284572.svg)](https://zenodo.org/badge/latestdoi/190284572)\n\nThe [ESP website](https://www.esp.cs.columbia.edu) contains the most\nup-to-date information on the ESP project. The\n[Documentation](https://www.esp.cs.columbia.edu/docs) page contains\ndetailed guides and video tutorials that will be released periodically\nto help users get the most out of ESP.\n\nESP is an open-source platform for heterogeneous SoC design and\nprototype on FPGA. It provides a flexible tile-based architecture\nbuilt on a multi-plane network-on-chip.\n\nIn addition to the architecture, ESP provides users with templates and\nscripts to create new accelerators from SystemC, Chisel, and C/C++.\nThe ESP design methodology eases the process of integrating processors\nand accelerators into an SoC by offering platform services, such as\nDMA, distributed interrupt, and run-time coherence selection, that\nhide the complexity of hardware and software integration from the\naccelerator designer.\n\nCurrently, ESP supports the integration of the\n[LEON3](https://www.gaisler.com/index.php/downloads/leongrlib) processor from\nGRLIB, the [Ariane](https://github.com/pulp-platform/ariane) core from the PULP\nPlatform, and the [Ibex](https://github.com/lowRISC/ibex) core from lowRISC.\nLEON3 implements the SPARC V8 32-bit ISA, Ariane implements the RISC-V\n64-bit ISA, and Ibex implements the RISC-V 32-bit ISA.\n\nIn addition to processor cores, ESP embeds accelerator design examples\ncreated with Stratus HLS in SystemC, Vivado HLS in C/C++ and Chisel.\n\nFurthermore, ESP can serve as a platform to integrate third-party IP\nblocks. For example, ESP integrates the NVIDIA Deep Learning\nAccelerator [NVDLA](http://nvdla.org/), which can be placed on any ESP\naccelerator tile.\n\n## Publications\n\nOverview paper:\n\n\u003e Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca\n\u003e Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca,\n\u003e Christian Pilato, Luca P. Carloni. _\"Agile SoC Development with Open\n\u003e ESP.\"_ IEEE/ACM International Conference On Computer Aided Design\n\u003e (ICCAD), 2020.\n\nThe [Publications](https://www.esp.cs.columbia.edu/pubs) page of the\nESP website contains the complete list of publications related to ESP.\n\n## Repository organization\n\nHere is a brief description of the main directories in the repository,\nplease refer to the READMEs inside each of them for more information.\n\n* `accelerators` contains multiple accelerator design and integration\n  flows, as well as many example accelerators.\n\n* `constraints` contains the constraints and attributes for each\n  supported FPGA board (or ASIC technology).\n\n* `socs` contains the working folders for launching all Make targets.\n  There is one working folder for each supported FPGA board (or ASIC\n  technology).\n\n* `rtl` contains the whole RTL code base, excluding the accelerators\n  RTL and the RTL generated in the working folder by the SoCGen and\n  SocketGen tools.\n\n* `soft` contains bootloader, Linux kernel and root file system, and\n  bare-metal library for each of the available processor cores. It\n  also contains bare-metal, user space and kernel space libraries for\n  invoking and managing accelerators.\n\n* `tech` is the destination of the RTL generated by the HLS-based and\n  Chisel-based accelerator design flows. It is also the destination of\n  the RTL generated with HLS for the SystemC implementation of the\n  cache hierarchy. The generated RTL is organized based on the target\n  FPGA (or ASIC) technology.\n\n* `tools` contains tools for design automation and for communicating\n  with an ESP SoC from a host machine.\n\n* `utils` contains various scripts and utilities, including the main\n  Makefiles, the RTL file lists, and the software toolchains\n  installation scripts.\n\n* `.cache` caches some compiled libraries so they only need to be\n  compiled once (e.g. Xilinx simulation libraries).\n\n## Stay tuned for the new features under development:\n\n   - Dynamic partial reconfiguration SoC flow\n   - Expanded support for ASIC design\n   - New platform services for programmable accelerators\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsld-columbia%2Fesp","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsld-columbia%2Fesp","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsld-columbia%2Fesp/lists"}