{"id":18257322,"url":"https://github.com/socxin/stm32wle5","last_synced_at":"2026-02-04T10:48:21.484Z","repository":{"id":131099196,"uuid":"313283371","full_name":"SoCXin/STM32WLE5","owner":"SoCXin","description":"L3 R6：ST Cortex-M4 LoRa SoC (STM32WLE4/STM32WLE5)","archived":false,"fork":false,"pushed_at":"2021-05-23T08:34:22.000Z","size":1365,"stargazers_count":0,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-02-14T17:55:20.035Z","etag":null,"topics":["cortex-m4","lora","qitas","soc","st"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/SoCXin.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":".github/FUNDING.yml","license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null},"funding":{"github":null,"patreon":null,"open_collective":null,"ko_fi":"qitas","tidelift":null,"community_bridge":null,"liberapay":null,"issuehunt":null,"otechie":null,"custom":null}},"created_at":"2020-11-16T11:40:49.000Z","updated_at":"2021-05-23T08:36:17.000Z","dependencies_parsed_at":"2023-04-13T11:03:34.545Z","dependency_job_id":null,"html_url":"https://github.com/SoCXin/STM32WLE5","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SoCXin%2FSTM32WLE5","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SoCXin%2FSTM32WLE5/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SoCXin%2FSTM32WLE5/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SoCXin%2FSTM32WLE5/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/SoCXin","download_url":"https://codeload.github.com/SoCXin/STM32WLE5/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247941702,"owners_count":21022036,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cortex-m4","lora","qitas","soc","st"],"created_at":"2024-11-05T10:25:39.862Z","updated_at":"2026-02-04T10:48:16.465Z","avatar_url":"https://github.com/SoCXin.png","language":null,"funding_links":["https://ko-fi.com/qitas"],"categories":[],"sub_categories":[],"readme":"# [STM32WLE5](https://github.com/SoCXin/STM32WLE5)\n\n[![sites](http://182.61.61.133/link/resources/SoC.png)](http://www.SoC.Xin)\n\n* [ST](https://www.st.com/zh/)：[Cortex-M4](https://github.com/SoCXin/Cortex)\n* [L3R6](https://github.com/SoCXin/Level) ：48 MHz  * 1.25 DMIPS/MHz\n\n## [简介](https://github.com/SoCXin/STM32WLE5/wiki)\n\n[STM32WLE5](https://github.com/SoCXin/STM32WLE5) 系列基于运行于48 MHz的Arm® Cortex®‐M4内核以及Semtech SX126x的sub-GHz无线电，是一种支持LoRa、(G)FSK、(G)MSK和BPSK调制的开放式平台。\n\n\n[![sites](docs/STM32WLE5.png)](https://my.st.com/content/my_st_com/zh/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-wireless-mcus/stm32wl-series/stm32wlex.html)\n\n### 关键特性\n\n* 150 MHz to 960 MHz ,LoRa®, FSK, MSK ,BPSK\n* 209MHz Cortex®-M4\n\n#### 封装规格\n\n* UFQFPN48（7x7mm）\n* UFBGA73（5x5mm）\n\n\n### [资源收录](https://github.com/SoCXin/STM32WLE5)\n\n* [参考文档](docs/)\n* [参考资源](src/)\n* [参考工程](project/)\n\n### [选型建议](https://github.com/SoCXin)\n\n[STM32WLE5](https://github.com/SoCXin/STM32WLE5)\n\n\n### [探索芯世界 www.SoC.xin](http://www.SoC.Xin)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsocxin%2Fstm32wle5","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fsocxin%2Fstm32wle5","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fsocxin%2Fstm32wle5/lists"}