{"id":18421999,"url":"https://github.com/spcl/hls_tutorial_examples","last_synced_at":"2025-08-20T12:31:28.645Z","repository":{"id":135158911,"uuid":"122743995","full_name":"spcl/hls_tutorial_examples","owner":"spcl","description":"Examples shown as part of the tutorial \"Productive parallel programming on FPGA with high-level synthesis\".","archived":false,"fork":false,"pushed_at":"2021-11-14T12:45:36.000Z","size":1327,"stargazers_count":196,"open_issues_count":0,"forks_count":46,"subscribers_count":17,"default_branch":"master","last_synced_at":"2024-12-06T10:50:30.808Z","etag":null,"topics":["fpga","high-level-synthesis","hls","intel-fpga","opencl","vivado-hls"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/spcl.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-02-24T13:44:24.000Z","updated_at":"2024-12-05T23:59:43.000Z","dependencies_parsed_at":null,"dependency_job_id":"f5764399-f4ad-4596-a19e-24c4fe6eb2d8","html_url":"https://github.com/spcl/hls_tutorial_examples","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fhls_tutorial_examples","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fhls_tutorial_examples/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fhls_tutorial_examples/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fhls_tutorial_examples/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/spcl","download_url":"https://codeload.github.com/spcl/hls_tutorial_examples/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":230423563,"owners_count":18223435,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","high-level-synthesis","hls","intel-fpga","opencl","vivado-hls"],"created_at":"2024-11-06T04:27:40.411Z","updated_at":"2024-12-19T11:12:08.493Z","avatar_url":"https://github.com/spcl.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"### Content\n\nThese are examples used in the tutorial _Productive Parallel Programming on FPGA\nwith High-Level Synthesis_, given at PPoPP'18, SC'18, SC'19, HiPEAC'20, SC'20,\nISC'21, and SC'21.\n\nFor comprehensive coverage of HLS transformations for HPC, we refer to our work\n_Transformations of High-Level Synthesis Codes for High-Performance Computing_,\n[available on arXiv](https://arxiv.org/abs/1805.08288) [1]. \n\n### Dependencies \n\nThese examples depend on [hlslib](https://github.com/definelicht/hlslib) as a\nsubmodule [2]. Make sure you clone with the `--recursive` flag, or run `git\nsubmodule update --init` after cloning.\n\nAll examples use CMake to configure and build both Xilinx and Intel kernels. The\nconfiguration relies on scripts to find the Xilinx and/or Intel tools on your\nsystem by looking for the `xocc` and `aoc` binaries, respectively. To ensure\nthat the tools are found, make sure these are on your `PATH`.\n\n### Building and running\n\nTo build the examples, create a build folder and configure it using CMake:\n\n```bash\nmkdir build\ncd build\ncmake ..\n```\n\nDepending on your installation of the Intel FPGA tools, you might have to\nspecify a board package available to your installation, e.g.,\n`-DINTEL_FPGA_BOARD=p520_hpc_sg280l`, to build the Intel emulation kernels.\n\nEach example has one or more synthesis targets (we recommend using a shell that\ncan autocomplete GNU make targets). For example, from your build directory:\n\n```bash\ncd example_0\nmake synthesize_example0\n```\n\nEach Xilinx synthesis target will also copy a `report.rpt`-file into the build\ndirectory, which you can inspect to get more detailed information about the\nresulting architecture.\n\nIntel synthesis targets are suffixed with `_intel`, and are not available for all\nexamples. Reports are generated in a subdirectory named after the kernel, e.g., `Example2/reports`. \n\n### References\n\n- [1] Johannes de Fine Licht, Maciej Besta, Simon Meierhans, and Torsten Hoefler. _\"Transformations of High-Level Synthesis Codes for High-Performance Computing.\"_ IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 32, Issue 5, 2021 ([arXiv link](https://arxiv.org/abs/1805.08288)).\n- [2] Johannes de Fine Licht and Torsten Hoefler. _\"hlslib: Software Engineering for Hardware Design\"_. arXiv preprint [arXiv:1910.04436](https://arxiv.org/abs/1910.04436) (2019).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fspcl%2Fhls_tutorial_examples","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fspcl%2Fhls_tutorial_examples","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fspcl%2Fhls_tutorial_examples/lists"}