{"id":13649130,"url":"https://github.com/spcl/pspin","last_synced_at":"2026-01-23T14:44:59.623Z","repository":{"id":47239391,"uuid":"357546275","full_name":"spcl/pspin","owner":"spcl","description":"PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing","archived":false,"fork":false,"pushed_at":"2023-02-22T09:51:37.000Z","size":9537,"stargazers_count":101,"open_issues_count":5,"forks_count":17,"subscribers_count":9,"default_branch":"master","last_synced_at":"2025-04-13T14:13:53.554Z","etag":null,"topics":["in-network-compute","networking","packet-processing","pulp","spin"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/spcl.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2021-04-13T12:33:16.000Z","updated_at":"2025-03-30T07:16:08.000Z","dependencies_parsed_at":"2024-01-14T11:00:04.110Z","dependency_job_id":"101029f5-692b-461a-80e8-15295fc36bff","html_url":"https://github.com/spcl/pspin","commit_stats":null,"previous_names":[],"tags_count":2,"template":false,"template_full_name":null,"purl":"pkg:github/spcl/pspin","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fpspin","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fpspin/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fpspin/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fpspin/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/spcl","download_url":"https://codeload.github.com/spcl/pspin/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fpspin/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28694457,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-23T14:15:13.573Z","status":"ssl_error","status_checked_at":"2026-01-23T14:09:05.534Z","response_time":59,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["in-network-compute","networking","packet-processing","pulp","spin"],"created_at":"2024-08-02T01:04:47.800Z","updated_at":"2026-01-23T14:44:59.386Z","avatar_url":"https://github.com/spcl.png","language":"SystemVerilog","funding_links":[],"categories":["SystemVerilog"],"sub_categories":[],"readme":"![GitHub Workflow Status](https://img.shields.io/github/workflow/status/spcl/pspin/CI)\n[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)\n[![License](https://img.shields.io/badge/License-SolderPad%200.51-blue.svg)](http://solderpad.org/licenses/SHL-0.51/)\n\n# PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing\n\n\u003cdiv align=\"center\"\u003e\u003cimg src=\"docs/overview.svg\" alt=\"PsPIN architecture overview\" /\u003e\u003c/div\u003e\n\n\nPsPIN [1] is an implementation of the sPIN programming model [2] based on PULP [3]. This repository includes the RTL code implementing PsPIN, the runtime software, and a set of examples to get started. We provide a toolchain that allows to define, build, and test new handlers through cycle-accurate simulations. \n\n\n**Simulation Workflow summary:** The RTL code is verilated into C++ modules that are compiled together with the functional models into two libraries: `libpspin.so` and `libpspin_debug.so`. To write your own handler, you need to define the handler code and a simulation driver. The handler code must be compiled with [RISC-V GCC](https://github.com/pulp-platform/pulp-riscv-gcc/tree/fe3ea0638f9e9bf563da8f2251d139727258f5aa). The simulation driver interfaces to `libpspin.so` for (1) initializing the simulation; (2) defining the content of L2 handler memory; (3) defining the handlers to offload; (4) defining and injecting packets to process; (5) handle events generated by the execution of the handlers (e.g., packets being sent or writes/reads to/from host memory). By linking against `libpspin_debug.so` you make the simulation a `waves.vcd` that can be explored with any value-change-dump editor (e.g., GTKWave http://gtkwave.sourceforge.net/).\n\n**Repo organization:** The repositority has the following structure:\n\n - `hw/`: Hardware components and simulation logic.\n   - `hw/deps/`: (RTL) Dependencies from the PULP platform (https://github.com/pulp-platform). Some of them have been adapted to fit in the PsPIN design. **License:** SolderPad 0.51.\n   - `hw/src/`: (RTL) PsPIN components. **License:** SolderPad 0.51.\n   - `hw/verilator_model/`: (functional) Components implementing the NIC model shown by the above figure. **License:** Apache 2.0.\n - `sw/`: Software components. **License:** Apache 2.0.\n   - `sw/pulp-sdk/`: Dependencies from the PULP SDK adapted to fit the PsPIN design. \n   - `sw/rules/`: Makefile rules used to ease simulutions setups and runs. \n   - `sw/runtime/`: HPUs runtime code and support functions for the handlers. \n   - `sw/script/`: utilities for extracting data from the simulation output. \n - `examples/`: Examples of sPIN handlers. **License:** Apache 2.0.\n    - `examples/*/driver/`. Simulation driver.\n    - `examples/*/handlers/`. Handlers code.\n\n## Getting started\n\nPlease check the docs: https://spcl.github.io/pspin/.\n\n## Citation\n\nPlease include this citation if you use this work as part of your project:\n\n```\n@inproceedings{pspin,\n\ttitle={A RISC-V in-network accelerator for flexible high-performance low-power packet processing},\n\tauthor={Di Girolamo, Salvatore and Kurth, Andreas and Calotoiu, Alexandru and Benz, Thomas and Schneider, Timo and Beranek, Jakub and Benini, Luca and Hoefler, Torsten},\n\tbooktitle={2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)},\n\tyear={2021}\n}\n```\n\n## References\n\n[1] Di Girolamo Salvatore, Kurth Andreas, Calotoiu Alexandru, Benz Thomas, Schneider Timo, Beranek Jakub, Benini Luca, Hoefler Torsten. \"A RISC-V in-network accelerator for flexible high-performance low-power packet processing.\" 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021. \n\n[2] Hoefler Torsten, Salvatore Di Girolamo, Konstantin Taranov, Ryan E. Grant, and Ron Brightwell. \"sPIN: High-performance streaming Processing in the Network.\" In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1-16. 2017.\n\n[3] Rossi, Davide, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. \"PULP: A parallel ultra low power platform for next generation IoT applications.\" In 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1-39. IEEE, 2015.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fspcl%2Fpspin","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fspcl%2Fpspin","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fspcl%2Fpspin/lists"}