{"id":18421985,"url":"https://github.com/spcl/rapidchiplet","last_synced_at":"2025-10-23T18:36:16.869Z","repository":{"id":206938768,"uuid":"717019882","full_name":"spcl/rapidchiplet","owner":"spcl","description":"A toolchain for rapid design space exploration of chiplet architectures","archived":false,"fork":false,"pushed_at":"2025-03-18T13:42:41.000Z","size":580,"stargazers_count":44,"open_issues_count":0,"forks_count":9,"subscribers_count":8,"default_branch":"main","last_synced_at":"2025-03-18T14:33:16.547Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/spcl.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2023-11-10T11:26:45.000Z","updated_at":"2025-03-18T13:42:45.000Z","dependencies_parsed_at":null,"dependency_job_id":"594f8de6-574d-4278-9c14-5b5ca32d3cf8","html_url":"https://github.com/spcl/rapidchiplet","commit_stats":null,"previous_names":["spcl/rapidchiplet"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Frapidchiplet","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Frapidchiplet/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Frapidchiplet/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Frapidchiplet/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/spcl","download_url":"https://codeload.github.com/spcl/rapidchiplet/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247670042,"owners_count":20976494,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-06T04:27:35.728Z","updated_at":"2025-10-23T18:36:16.849Z","avatar_url":"https://github.com/spcl.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RapidChiplet\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"misc/main_overview.svg\"\u003e\n\u003c/p\u003e\n\n## Setup Guide\n\nClone the RapidChiplet repository:\n```bash\ngit clone https://github.com/spcl/rapidchiplet.git\n```\n\nInstall all requirements using pip:\n```bash\ncd rc \npip install -r requirements.txt\n```\n\nBuild the BookSim2 [1,2] simulator:\n```bash\ncd booksim2/src\nmake\ncd ../../\n```\n\nBuild Netrace [3,4]\n```bash\ncd netrace\ngcc export_trace.c netrace.c -o export_trace\ncd ../\n```\n\n## Reproducing Results from the RapidChiplet Paper\n\n```bash\npython3 reproduce_paper_results.py\n```\n- Note that this script runs for almost one day.\n- The results might slightly differ from the paper due to different system specifications.\n- The plots that appear in the paper in Figure 4 (right), Figure 5, and Figure 6 will be stored in the `./plots/` directory.\n- The chip visualization that appears in the paper in Figure 4 (left) will be stored in the `./images/` directory.\n\n## RapidChiplet Core\n\n### Inputs\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"misc/input_overview.svg\" style=\"width: 100%; height: auto;\"\u003e\n\u003c/p\u003e\n\n\nConfigure your chip design using the different input files. Check out the example files in `./inputs/` to get started.\n\nWe provide the following input generation scripts for more complex input-files that cannot easily be written by hand:\n\n**generate_routing.py**: Generates a routing table for a given chip design\n\n```bash\npython3 generate_routing.py -df inputs/designs/\u003cdesign_file\u003e -rtf \u003crouting_table_file\u003e -ra \u003crouting_algorithm\u003e\n```\n- The `\u003cdesign file\u003e` points to all inputs that the routing table generator needs (chiplets, placement, topology).\n- The `\u003crouting_table_file\u003e` is the name under which the resulting routing table is stored (in `inputs/routing_tables/`).\n- `\u003crouting algorithm\u003e` specifies the routing algorithm to be used. We currently support two routing algorithms:\n  - `splif`: Shortest Path Lowest ID first\n  - `sptmr`: Shortest Path Turn Model Random\n\n**generate_traffic.py**: Generate a synthetic traffic pattern for a given chip design\n\n```bash\npython3 generate_traffic.py -df inputs/designs/\u003cdesign_file\u003e -tf \u003ctraffic_file\u003e -tp \u003ctraffic_pattern\u003e -par \u003cparameters\u003e\n```\n- The `\u003cdesign file\u003e` points to all inputs that the traffic generator needs (chiplets, placement).\n- The `\u003ctraffic_file\u003e` is the name under which the resulting traffic pattern is stored (in `/inputs/traffic_by_chiplet/` and `inputs/traffic_by_unit/`).\n- `\u003ctraffic_pattern\u003e` specifies the traffic pattern to be generated. We currently support four traffic patterns: `random_uniform`, `transpose`, `permutation`, `hotspot`.\n- `\u003cparameters\u003e` are specific to the selected traffic pattern.\n\n### Executing RapidChiplet\n\n```bash\npython3 rapidchiplet.py -df inputs/designs/\u003cdesign_file\u003e -rf \u003cresults_file\u003e [-as] [-ps] [-ls] [-c] [-l] [-t]\n```\n- The `\u003cdesign_file\u003e` points to all inputs that are required\n- The `\u003cresults_file\u003e` specifies the name, under which the results are stored (in `/results/`).\n- The optional flags are used to enable the computation of different metrics: area summary (`-as`), power summary (`-ps`), link summary (`-ls`), manufacturing cost (`-c`), latency (`-l`), throughput (`-t`).\n\n## Cycle-based Simulations using BookSim\n\nTo export a design to BookSim and gather the results, simply run `rapidchiplet.py` with the `-bs` flag:\n\n```bash\npython3 rapidchiplet.py -df inputs/designs/\u003cdesign_file\u003e -rf \u003cresults_file\u003e -bs\n```\n- The `\u003cdesign_file\u003e` points to all inputs that are required.\n- The `\u003cresults_file\u003e` specifies the name, under which the results are stored (in `/results/`).\n\n## Automated Design Space Exploration\n\n### Inputs\n\nSpecify parameters and parameter-ranges for your design space exploration in an experiment-file in the `./experiments/` directory. Check out the provided example files to get started.\n\n\n### Running the Automated DSE\n\n```bash\npython3 run_experiment.py -e experiments/\u003cexperiment_file\u003e\n```\n\nThis script generates one results-file for each combination of input parameters. All result-files are stored in `./results/`.\n\n## Exporting Network Traces using Netrace\n\n### Inputs\n\nDownload the traces from the netrace website [5] and store them in `./netrace/traces_in/`.\n\n### Export traces\n\nIn a first step, export the traces from the netrace format into an intermediate format:\n\n```bash\ncd netrace\n./export_trace traces_in/\u003ctrace_name\u003e.tra.bz2 \u003ctrace_region_id\u003e \u003cpacket_limit\u003e \u003e traces_out/\u003ctrace_name\u003e.json\ncd ../\n```\n\n- Netrace traces contain one or multiple trace regions. Use the `\u003ctrace_region_id\u003e` argument to specify the region to export. If you want to export the whole trace, omit this argument.\n- Some Netrace traces are very long. If you only want to export a partial trace region, use the `\u003cpacket_limit\u003e` argument to pass the maximum number of packets that should be exported.\n\nIn a second step, the trace is parsed into the RapidChiplet format:\n\n```bash\npython3 parse_netrace_trace.py -df inputs/designs/\u003cdesign_file\u003e -if netrace/traces_out/\u003ctrace_name\u003e.json -of \u003ctrace_name\u003e.json\n```\n\n- The `\u003cdesign file\u003e` points to all inputs that the trace parser needs.\n- The arguments `-if` and `-of` refer to the input-trace-file (in the intermediate format) and the output-trace-file (in the output format). The output trace file is stored in `inputs/traces/`.\n\n\n## Visualization of Inputs and Results\n\n### Visualizing Inputs\n\nVisualize a complete design by running\n\n```bash\npython3 visualizer.py -df inputs/designs/\u003cdesign_name\u003e [-sci] [-spi]\n```\n- You can show chiplet-IDs and PHY-IDs by passing the `-sci` and `-spi` flags respectively.\n\n\nYou can also visualize a single chiplet by running\n\n```bash\npython3 visualizer.py -cf inputs/chiplets/\u003cchiplet_file\u003e -cn \u003cchiplet_name\u003e\n```\n\n- `\u003cchiplet_file\u003e` is an input file which potentially specifies multiple chiplets and `\u003cchiplet_name\u003e` is the name of one specific chiplet within this file.\n\n### Visualizing Results\n\nVisualize the results by running:\n\n```bash\npython3 create_plots.py -rf results/\u003cresults-file\u003e -pt \u003cplot_type\u003e\n```\n\n- The `\u003cresults_file\u003e` contains the results you want to visualize.\n- Currently, only one plot type, namely, `latency_vs_load` is supported, but more will be added soon.\n\n\n## References\n\n[1] Jiang, N., Becker, D.U., Michelogiannakis, G., Balfour, J., Towles, B., Shaw, D.E., Kim, J. and Dally, W.J., 2013, April. A detailed and flexible cycle-accurate network-on-chip simulator. In 2013 IEEE international symposium on performance analysis of systems and software (ISPASS) (pp. 86-96). IEEE.\n\n[2] https://github.com/booksim/booksim2\n\n[3] Hestness, J., Grot, B. and Keckler, S.W., 2010, December. Netrace: dependency-driven trace-based network-on-chip simulation. In Proceedings of the Third International Workshop on Network on Chip Architectures (pp. 31-36).\n\n[4] https://github.com/booksim/netrace\n\n[5] https://www.cs.utexas.edu/~netrace/\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fspcl%2Frapidchiplet","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fspcl%2Frapidchiplet","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fspcl%2Frapidchiplet/lists"}