{"id":18421964,"url":"https://github.com/spcl/stencilflow","last_synced_at":"2025-06-16T03:40:16.490Z","repository":{"id":47149097,"uuid":"269585710","full_name":"spcl/stencilflow","owner":"spcl","description":null,"archived":false,"fork":false,"pushed_at":"2021-09-15T21:13:38.000Z","size":31959,"stargazers_count":16,"open_issues_count":2,"forks_count":3,"subscribers_count":6,"default_branch":"master","last_synced_at":"2025-03-22T19:45:47.065Z","etag":null,"topics":["fpga","high-level-synthesis","hls","intel-fpga"],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/spcl.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-06-05T09:24:46.000Z","updated_at":"2025-03-06T18:52:08.000Z","dependencies_parsed_at":"2022-08-02T18:16:02.352Z","dependency_job_id":null,"html_url":"https://github.com/spcl/stencilflow","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fstencilflow","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fstencilflow/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fstencilflow/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/spcl%2Fstencilflow/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/spcl","download_url":"https://codeload.github.com/spcl/stencilflow/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247670016,"owners_count":20976492,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","high-level-synthesis","hls","intel-fpga"],"created_at":"2024-11-06T04:27:28.147Z","updated_at":"2025-04-07T14:32:05.559Z","avatar_url":"https://github.com/spcl.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"Introduction\n============\n\nThis repository implements an end-to-end stack that compiles a high-level\ndescription of a stencil program to hardware. Dependencies between stencil\noperators are resolved by streaming fine-grained results directly between\nprocessing elements on the chip. \n\nPrerequisites\n=============\n\nTo run the code, the following software must be available:\n- Python 3.6.x or newer.\n- The `virtualenv` module (installed with `pip install virtualenv`).\n- A C++17-capable compiler (e.g., GCC 7.x or Clang 6.x).\n- One or both FPGA compilers:\n  - Intel FPGA OpenCL SDK (tested with 18.1.1 and 19.1)\n  - Xilinx Vitis (tested with 2020.2) \n\nSetup\n=====\n\nSourcing the script `setup_virtualenv.sh` will setup a virtualenv with all the\nmodules required to run StencilFlow, including the relevant version of DaCe:\n\n```bash\nsource setup_virtualenv.sh\n```\n\nRunning\n=======\n\nTo run the end-to-end flow on an input JSON file, the executable\n`bin/run_program.py` can be used. Example usage:\n\n```bash\nbin/run_program.py test/stencils/jacobi3d_32x32x32_8itr_8vec.json emulation -compare-to-reference\n```\n\nThis will compile the FPGA kernel for Intel's emulation flow, execute it, build\na reference CPU program, run both, and verify that the results match.\n\nThe generated program will be located in `.dacecache/\u003ckernel name\u003e`, with the\nkernel source files themselves in:\n\n```bash\n.dacecache/\u003ckernel name\u003e/src/intel_fpga/device\n```\n\nVerification\n------------\n\nFor programs using the \"shrink\" boundary conditions, the borders will\nintentionally have invalid results in them. To do validation in this scenario,\nuse the `-halo=3` flag to specify how large of a halo should be ignored in\nvalidation in each dimension.\n\nProgram description\n-------------------\n\nExamples of program descriptions are located in `test/stencils`, including for\n2D and 3D stencils, vectorization, and lower dimensional inputs.\n\nExecutables\n-----------\n\nAll executables are included in the `bin` subfolder, and have documented command\nline interfaces.\n\nTests\n=====\n\nThe repository ships with a number of tests that verify various aspects of\nfunctionality. These can be run with:\n\n```bash\ntest/test_stencil.py\n```\n\nIt is a known issue that launching multiple Intel FPGA kernels in quick\nsuccession (such as is done in the tests) can sometimes fail sporadically,\nseemingly due to file I/O issues. Running individual programs should never fail.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fspcl%2Fstencilflow","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fspcl%2Fstencilflow","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fspcl%2Fstencilflow/lists"}