{"id":15141505,"url":"https://github.com/standardsemiconductor/lion","last_synced_at":"2025-07-16T05:39:12.198Z","repository":{"id":42659192,"uuid":"339923019","full_name":"standardsemiconductor/lion","owner":"standardsemiconductor","description":"Where Lions Roam: RISC-V on the VELDT","archived":false,"fork":false,"pushed_at":"2024-08-03T07:53:28.000Z","size":331,"stargazers_count":258,"open_issues_count":3,"forks_count":16,"subscribers_count":11,"default_branch":"main","last_synced_at":"2025-05-19T19:11:23.575Z","etag":null,"topics":["clash","haskell","risc-v","veldt"],"latest_commit_sha":null,"homepage":"https://hackage.haskell.org/package/lion","language":"Haskell","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/standardsemiconductor.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-02-18T03:18:12.000Z","updated_at":"2025-05-17T16:22:07.000Z","dependencies_parsed_at":"2024-01-16T06:44:26.684Z","dependency_job_id":"07f2ef37-2358-4336-9301-05771eb3ffdd","html_url":"https://github.com/standardsemiconductor/lion","commit_stats":null,"previous_names":[],"tags_count":5,"template":false,"template_full_name":null,"purl":"pkg:github/standardsemiconductor/lion","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/standardsemiconductor%2Flion","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/standardsemiconductor%2Flion/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/standardsemiconductor%2Flion/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/standardsemiconductor%2Flion/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/standardsemiconductor","download_url":"https://codeload.github.com/standardsemiconductor/lion/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/standardsemiconductor%2Flion/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":265485170,"owners_count":23774441,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["clash","haskell","risc-v","veldt"],"created_at":"2024-09-26T09:01:06.410Z","updated_at":"2025-07-16T05:39:12.163Z","avatar_url":"https://github.com/standardsemiconductor.png","language":"Haskell","readme":"# Where Lions Roam: RISC-V on the VELDT\n\n[![Haskell CI](https://github.com/standardsemiconductor/lion/actions/workflows/haskell.yml/badge.svg?branch=main)](https://github.com/standardsemiconductor/lion/actions/workflows/haskell.yml)\n[![Hackage][hackage-badge]][hackage]\n[![Hackage Dependencies][hackage-deps-badge]][hackage-deps]\n\nLion is a formally verified, 5-stage pipeline [RISC-V](https://riscv.org) core. Lion targets the [VELDT FPGA development board](https://standardsemiconductor.com) and is written in Haskell using [Clash](https://clash-lang.org).\n\nThis repository contains four parts:\n  1. The Lion library: a pipelined RISC-V core.\n  2. [lion-formal](lion-formal): formally verify the core using [riscv-formal](https://github.com/standardsemiconductor/riscv-formal/tree/lion).\n  3. [lion-soc](lion-soc): a System-on-Chip demonstrating usage of the Lion core on the VELDT.\n  4. [lion-metric](lion-metric): Observe Yosys synthesis metrics on the Lion Core.\n\n## Lion library\n### Usage:\n1. Add `lion` to build depends section of Cabal file\n2. import module in source files `import Lion.Core`\n\nWhen connecting the `core` to memory and peripherals, ensure single cycle latency.\n\n## Clone the repository\n1. `git clone https://github.com/standardsemiconductor/lion.git`\n2. `cd lion`\n3. `git submodule update --init`\n\n## Features\n### Current Support\n* Architecture: RV32I (no FENCE, ECALL, EBREAK)\n* Configurable ALU adder and subtractor: use a generic (+) and (-) or SB_MAC16 hard IP\n\n### Future Support \n**All features will be added in a configurable manner extending the base RV32I configuration noted above**\n* Zicsr, Control and Status Register (CSR) Instructions\n* CSR registers\n* RV32IM\n\nCheck out the [Lion Development project](https://github.com/standardsemiconductor/lion/projects/1) to see which features are in progress.\n\n## References and Additional Resources\n* [RISC-V Specifications](https://riscv.org/technical/specifications/)\n* [Computer Architecture: A Quantitative Approach 6th Ed.](https://www.elsevier.com/books/computer-architecture/hennessy/978-0-12-811905-1)\n\n[hackage]:            \u003chttps://hackage.haskell.org/package/lion\u003e\n[hackage-badge]:      \u003chttps://img.shields.io/hackage/v/lion.svg?color=success\u003e\n[hackage-deps-badge]: \u003chttps://img.shields.io/hackage-deps/v/lion.svg\u003e\n[hackage-deps]:       \u003chttp://packdeps.haskellers.com/feed?needle=lion\u003e\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fstandardsemiconductor%2Flion","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fstandardsemiconductor%2Flion","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fstandardsemiconductor%2Flion/lists"}