{"id":28140221,"url":"https://github.com/stillwater-sc/risc-v-tensorcore","last_synced_at":"2026-01-25T15:02:51.905Z","repository":{"id":48292147,"uuid":"380509965","full_name":"stillwater-sc/RISC-V-TensorCore","owner":"stillwater-sc","description":"Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra","archived":false,"fork":false,"pushed_at":"2021-12-19T12:19:41.000Z","size":146,"stargazers_count":54,"open_issues_count":0,"forks_count":14,"subscribers_count":4,"default_branch":"main","last_synced_at":"2025-05-14T18:11:31.358Z","etag":null,"topics":["reproducible-computation","risc-v64","vector-processor"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/stillwater-sc.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":".github/FUNDING.yml","license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null},"funding":{"github":["stillwater-sc"]}},"created_at":"2021-06-26T13:36:27.000Z","updated_at":"2025-05-11T15:41:24.000Z","dependencies_parsed_at":"2022-08-28T02:41:41.833Z","dependency_job_id":null,"html_url":"https://github.com/stillwater-sc/RISC-V-TensorCore","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/stillwater-sc/RISC-V-TensorCore","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stillwater-sc%2FRISC-V-TensorCore","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stillwater-sc%2FRISC-V-TensorCore/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stillwater-sc%2FRISC-V-TensorCore/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stillwater-sc%2FRISC-V-TensorCore/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/stillwater-sc","download_url":"https://codeload.github.com/stillwater-sc/RISC-V-TensorCore/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stillwater-sc%2FRISC-V-TensorCore/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28754807,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-25T13:59:49.818Z","status":"ssl_error","status_checked_at":"2026-01-25T13:59:33.728Z","response_time":113,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["reproducible-computation","risc-v64","vector-processor"],"created_at":"2025-05-14T18:11:01.349Z","updated_at":"2026-01-25T15:02:51.895Z","avatar_url":"https://github.com/stillwater-sc.png","language":"Verilog","funding_links":["https://github.com/sponsors/stillwater-sc"],"categories":[],"sub_categories":[],"readme":"# RISC-V TensorCore\n\nThe goals of the RISC-V TensorCore project are to create RISC-V V-extension-based hardware accelerators that leverage\ncustom numerics to gain energy-efficiency, performance, reproducibility, or reliable computations for robotics, model-predictive\ncontrol, AI/ML, Reinforcement Learning, data acquisition and signal processing applications.\n\nAs many embedded intelligence applications will reside on the edge, and hardware experimentation requires a cost-effective\nand flexible design environment, most of the vector engines presented here are targeted as softcores on different FPGA platforms.\nAs the reconfigurability of an FPGA adds overhead to the realization of the logic for a computational transformation, it\nis paramount for energy-efficiency that the computational engine takes full advantage of the hardmacros available in the FPGA.\nThe micro-architecture of a vector engine maps well to the DSP-slice architecture of most FPGAs, hence the selection of vector\narchitectures to deliver on custom compute engines with custom numerics.\n\n\nFurthermore, when introducing custom numerics, the language support for these new types will always lag by many years, and sometimes\nthe language standard committee will never be motivated to adapt. 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