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Implementations"],"sub_categories":["网络服务_其他","Cores"],"readme":"# The NEORV32 RISC-V Processor\n\n[![datasheet (pdf)](https://img.shields.io/badge/Data%20Sheet-PDF-ffbd00?longCache=true\u0026style=flat\u0026logo=asciidoctor\u0026colorA=273274)](https://github.com/stnolting/neorv32/releases/download/nightly_release/NEORV32-nightly.pdf)\n[![datasheet (html)](https://img.shields.io/badge/-HTML-ffbd00?longCache=true\u0026style=flat)](https://stnolting.github.io/neorv32)\n[![userguide (pdf)](https://img.shields.io/badge/User%20Guide-PDF-ffbd00?longCache=true\u0026style=flat\u0026logo=asciidoctor\u0026colorA=273274)](https://github.com/stnolting/neorv32/releases/download/nightly_release/NEORV32_UserGuide-nightly.pdf)\n[![userguide (html)](https://img.shields.io/badge/-HTML-ffbd00?longCache=true\u0026style=flat)](https://stnolting.github.io/neorv32/ug)\n[![doxygen](https://img.shields.io/badge/SW_API-HTML-ffbd00?longCache=true\u0026style=flat\u0026logo=Doxygen\u0026colorA=273274)](https://stnolting.github.io/neorv32/sw/files.html)\n[![license](https://img.shields.io/github/license/stnolting/neorv32?label=License\u0026longCache=true\u0026style=flat\u0026logo=bsd)](https://github.com/stnolting/neorv32/blob/main/LICENSE)\n\nThe NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** built around the NEORV32\n[RISC-V](https://riscv.org/) CPU that is written in **platform-independent VHDL**. The processor is intended as auxiliary\ncontroller in larger SoC designs or as tiny and customized microcontroller. The project is intended to work _out of the box_\nand targets FPGA / RISC-V beginners as well as experienced users.\n\n![neorv32 Overview](docs/figures/neorv32_processor.png)\n\n### Key Features\n\n- [x] all-in-one package: **CPU** + **SoC** + **Software Framework** + **Test Infrastructure**\n- [x] fully self-contained - no external source dependencies\n- [x] completely described in behavioral, platform-independent VHDL - **no** primitives, macros, attributes, etc.\n- [x] technology friendly; e.g. all internal memories can be mapped to FPGA or ASIC primitives\n- [x] extensive CPU \u0026 SoC configuration options for adapting to application requirements\n- [x] aims to be as small as possible while being as RISC-V-compliant as possible\n- [x] optimized for high clock frequencies to ease integration and timing closure\n- [x] from zero to `printf(\"hello world\");` - completely open-source and documented\n- [x] easy to use – intended to work _out of the box_\n\n* :recycle: Looking for an **all-Verilog** version? Have a look at the [auto-conversion setup](rtl/verilog).\n* :mag: [Continuous integration](#project-status) to check for regressions (including RISC-V ISA compatibility check using RISCOF).\n* :open_file_folder: [Exemplary setups](https://github.com/stnolting/neorv32-setups) and\n[community projects](https://github.com/stnolting/neorv32-setups/blob/main/README.md#Community-Projects)\ntargeting various FPGA boards and toolchains to get started.\n* :package: The entire processor is also available as [Vivado IP Block](https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block).\n* :kite: Upstream [Zephyr](https://docs.zephyrproject.org/latest/boards/others/neorv32/doc/index.html) and\n[FreeRTOS](https://github.com/stnolting/neorv32-freertos) operating system support.\n* :penguin: Capable of [running nommu-Linux](https://github.com/14sea/see_neorv32_run_linux).\n* :building_construction: [LiteX](https://github.com/enjoy-digital/litex/wiki/CPUs#risc-v---neorv32) SoC builder integration.\n* :gear: [MicroPython](https://github.com/stnolting/neorv32-micropython) port, [Ada](https://github.com/GNAT-Academic-Program/neorv32-hal) support, and\n[Rust](https://crates.io/crates/embassy-neorv32) integration via Embassy framework.\n* :desktop_computer: Pre-configured [Eclipse project](https://stnolting.github.io/neorv32/ug/#_eclipse_ide) for developing and debugging code using an IDE.\n* :label: The project's change log is available in [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md).\n* :rocket: Check out the [quick links below](#getting-started) and the\n[User Guide](https://stnolting.github.io/neorv32/ug/) to get started.\n* :books: For detailed information see the [online documentation](https://stnolting.github.io/neorv32/).\n\n### Project Status\n\n[![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true\u0026style=flat\u0026logo=GitHub)](https://github.com/stnolting/neorv32/releases)\n[![commits-since-latest-release](https://img.shields.io/github/commits-since/stnolting/neorv32/latest?longCache=true\u0026style=flat\u0026logo=GitHub)](https://github.com/stnolting/neorv32/activity)\n\n| Task | CI Status |\n|:-----|:----------|\n| GitHub pages         | [![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32\u0026longCache=true\u0026style=flat-square\u0026url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html\u0026logo=GitHub)](https://stnolting.github.io/neorv32) |\n| Documentation        | [![Documentation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Documentation.yml?branch=main\u0026longCache=true\u0026style=flat-square\u0026label=Documentation\u0026logo=Github%20Actions\u0026logoColor=fff)](https://github.com/stnolting/neorv32/actions/workflows/Documentation.yml) |\n| Processor check      | [![Processor](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Processor.yml?branch=main\u0026longCache=true\u0026style=flat-square\u0026label=Processor%20Check\u0026logo=Github%20Actions\u0026logoColor=fff)](https://github.com/stnolting/neorv32/actions/workflows/Processor.yml) |\n| Verilog conversion   | [![Verilog Conversion](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Verilog.yml?branch=main\u0026longCache=true\u0026style=flat-square\u0026label=Verilog%20Conversion\u0026logo=Github%20Actions\u0026logoColor=fff)](https://github.com/stnolting/neorv32/actions/workflows/Verilog.yml)\n| RISC-V compatibility | [![riscv-arch-test](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/riscv-arch-test.yml?branch=main\u0026longCache=true\u0026style=flat-square\u0026label=RISC-V%20Compatibility%20Test\u0026logo=Github%20Actions\u0026logoColor=fff)](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |\n\nThe processor passes the official RISC-V architecture compatibility tests. It can successfully run _any_ C program\nincluding CoreMark and FreeRTOS and can be synthesized for _any_ target technology - [tested](https://github.com/stnolting/neorv32-setups)\non AMD, Intel, Lattice, Microchip, Gowin and Cologne Chip FPGAs. The processor has also been taped out several times as an ASIC.\n\n\n## Features\n\nThe NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU.\nBy using generics the design is highly configurable and allows a flexible customization to tailor the\nsetup according to your needs. Note that all of the following SoC modules are entirely _optional_.\n\n**CPU Core(s)**\n\n* [![RISCV-ARCHID](https://img.shields.io/badge/RISC--V%20Architecture%20ID-19-000000.svg?longCache=true\u0026style=flat-square\u0026logo=riscv\u0026colorA=273274\u0026colorB=fbb517)](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n* RISC-V 32-bit little-endian pipelined/multi-cycle modified-Harvard architecture\n* Single-core or SMP dual-core configuration\n* configurable instruction sets and extensions:\n\\\n`RV32`\n[`I`](https://stnolting.github.io/neorv32/#_i_isa_extension)\n[`E`](https://stnolting.github.io/neorv32/#_e_isa_extension)\n[`M`](https://stnolting.github.io/neorv32/#_m_isa_extension)\n[`A`](https://stnolting.github.io/neorv32/#_a_isa_extension)\n[`C`](https://stnolting.github.io/neorv32/#_c_isa_extension)\n[`B`](https://stnolting.github.io/neorv32/#_b_isa_extension)\n[`U`](https://stnolting.github.io/neorv32/#_u_isa_extension)\n[`X`](https://stnolting.github.io/neorv32/#_x_isa_extension)\n[`Zaamo`](https://stnolting.github.io/neorv32/#_zaamo_isa_extension)\n[`Zalrsc`](https://stnolting.github.io/neorv32/#_zalrsc_isa_extension)\n[`Zcb`](https://stnolting.github.io/neorv32/#_zcb_isa_extension)\n[`Zba`](https://stnolting.github.io/neorv32/#_zba_isa_extension)\n[`Zbb`](https://stnolting.github.io/neorv32/#_zbb_isa_extension)\n[`Zbkb`](https://stnolting.github.io/neorv32/#_zbkb_isa_extension)\n[`Zbkc`](https://stnolting.github.io/neorv32/#_zbkc_isa_extension)\n[`Zbkx`](https://stnolting.github.io/neorv32/#_zbkx_isa_extension)\n[`Zbs`](https://stnolting.github.io/neorv32/#_zbs_isa_extension)\n[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_isa_extension)\n[`Zibi`](https://stnolting.github.io/neorv32/#_zibi_isa_extension)\n[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_isa_extension)\n[`Zicond`](https://stnolting.github.io/neorv32/#_zicond_isa_extension)\n[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_isa_extension)\n[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_isa_extension)\n[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_isa_extension)\n[`Zimop`](https://stnolting.github.io/neorv32/#_zimop_isa_extension)\n[`Zkn`](https://stnolting.github.io/neorv32/#_zkn_isa_extension)\n[`Zknd`](https://stnolting.github.io/neorv32/#_zknd_isa_extension)\n[`Zkne`](https://stnolting.github.io/neorv32/#_zkne_isa_extension)\n[`Zknh`](https://stnolting.github.io/neorv32/#_zknh_isa_extension)\n[`Zkt`](https://stnolting.github.io/neorv32/#_zkt_isa_extension)\n[`Zks`](https://stnolting.github.io/neorv32/#_zks_isa_extension)\n[`Zksed`](https://stnolting.github.io/neorv32/#_zksed_isa_extension)\n[`Zksh`](https://stnolting.github.io/neorv32/#_zksh_isa_extension)\n[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_isa_extension)\n[`Sdext`](https://stnolting.github.io/neorv32/#_sdext_isa_extension)\n[`Sdtrig`](https://stnolting.github.io/neorv32/#_sdtrig_isa_extension)\n[`Smcntrpmf`](https://stnolting.github.io/neorv32/#_smcntrpmf_isa_extension)\n[`Smpmp`](https://stnolting.github.io/neorv32/#_smpmp_isa_extension)\n[`Xcfu`](https://stnolting.github.io/neorv32/#_xcfu_isa_extension)\n* compatible to subsets of the RISC-V \"Unprivileged ISA Specification\" and \"Privileged Architecture Specification\"\n* `machine` and `user` privilege modes\n* implements **all** standard RISC-V exceptions and interrupts + 16 fast interrupt request channels as NEORV32-specific extension\n* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu) as custom `Xcfu` ISA extension)\nfor **custom RISC-V instructions**\n\n**Memories**\n\n* tightly-coupled data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) \u0026\n[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) and\ncaches ([iCACHE](https://stnolting.github.io/neorv32/#_instruction_cache_icache) \u0026\n[dCACHE](https://stnolting.github.io/neorv32/#_data_cache_dcache))\n* pre-installed bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface;\nallows booting application code via UART, I²C or SPI flash and SD card\n\n**Timers and Counters**\n\n* RISC-V-compatible core-local interruptor ([CLINT](https://stnolting.github.io/neorv32/#_core_local_interruptor_clint))\n* 32-bit general purpose timer ([GPTMR](https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr)) with up to 16 individual timer slices\n* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))\n\n**Input / Output**\n\n* standard serial interfaces: 2x [UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0),\n[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi) (SPI host),\n[SDI](https://stnolting.github.io/neorv32/#_serial_data_interface_controller_sdi) (SPI device),\n[TWI](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi) (I²C host),\n[TWD](https://stnolting.github.io/neorv32/#_two_wire_serial_device_controller_twd) (I²C device),\n[ONEWIRE](https://stnolting.github.io/neorv32/#_one_wire_serial_interface_controller_onewire) (1-wire host)\n* up to 32 general purpose IOs ([GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio), interrupt-capable)\nand up to 32 individual [PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm) channels\n* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly control NeoPixel(TM) LEDs\n\n**SoC Connectivity**\n\n* 32-bit external bus interface - Wishbone-compatible\n([XBUS](https://stnolting.github.io/neorv32/#_processor_external_bus_interface_xbus));\n[bridge](https://github.com/stnolting/neorv32/blob/main/rtl/system_integration) for AXI4-compatible interfaces\n* stream link interface with independent RX and TX channels - AXI4-Stream-compatible\n([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))\n\n**Advanced**\n\n* true-random number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng)) based\non the [neoTRNG](https://github.com/stnolting/neoTRNG)\n* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))\nfor custom tightly-coupled co-processors, accelerators or interfaces\n* direct memory access controller ([DMA](https://stnolting.github.io/neorv32/#_direct_memory_access_controller_dma)) for CPU-independent\ndata transfers and conversions\n* RVFI-compatible [trace port](https://stnolting.github.io/neorv32/#_execution_trace_port)\nfor advanced debugging, profiling or verification\n\n**Debugging**\n\n* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via standard JTAG interface\n* compatible to the \"Minimal RISC-V Debug Specification Version 1.0\"\n* compatible with **OpenOCD**, **GDB** and **Segger Embedded Studio**\n* RISC-V [trigger module](https://stnolting.github.io/neorv32/#_trigger_module) for hardware-assisted break- and watchpoints\n* optional JTAG authentication module to implement custom security mechanisms\n* execution trace buffer ([TRACER](https://stnolting.github.io/neorv32/#_execution_trace_buffer_tracer))\n\n### Size ad Performance\n\nThe NEORV32 processor is optimized for minimal size. However, the actual size (silicon area or FPGA resources)\ndepends on the specific configuration. For example, an RTOS-capable setup based on a `rv32imc_Zicsr_Zicntr` CPU\nconfiguration requires about 2300 LUTs and 1000 FFs and can run at up to 130 MHz (implementation results for an\nAltera Cyclone IV E `EP4CE22F17C6` FPGA). This configuration provides a CoreMark score of 95.23 (0.9523 CoreMarks/MHz).\n\nMore information regarding the CPU performance can be found in the\n[Data Sheet: Performance](https://stnolting.github.io/neorv32/#_performance).\n\n\n## Getting Started\n\nThis overview provides some *quick links* to the most important sections of the\n[online Data Sheet](https://stnolting.github.io/neorv32) and the [online User Guide](https://stnolting.github.io/neorv32/ug).\n\n### :mag: [NEORV32 Project](https://stnolting.github.io/neorv32/#_overview) - An Introduction\n\n* [Key Features](https://stnolting.github.io/neorv32/#_project_key_features) - what makes it special\n* [Structure](https://stnolting.github.io/neorv32/#_project_folder_structure) - folders, RTL files and compile order\n* [File-List Files](https://stnolting.github.io/neorv32/#_file_list_files) - to simplify HDL setup\n* [Metrics](https://stnolting.github.io/neorv32/#_performance) - FPGA implementation and performance evaluation\n* [RISC-V Compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs and what is not\n\n### :desktop_computer: [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - The SoC\n\n* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor\n* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - processor/CPU configuration options\n* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and address mapping\n* [Boot Configuration](https://stnolting.github.io/neorv32/#_boot_configuration) - how to make the processor start executing\n* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - IO/peripheral modules and memories\n* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - in-system debugging via JTAG\n\n### :abacus: [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - The Core\n\n* [Architecture](https://stnolting.github.io/neorv32/#_architecture) - a look under the hood\n* [Full Virtualization](https://stnolting.github.io/neorv32/#_full_virtualization) - execution safety\n* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available (RISC-V) ISA extensions\n* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers\n* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions\n\n### :floppy_disk: [Software Framework](https://stnolting.github.io/neorv32/#_software_framework) - The Software Ecosystem\n\n* [Example Programs](https://github.com/stnolting/neorv32/tree/main/sw/example) - examples how to use the processor's IO/peripheral modules\n* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals\n* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - _doxygen_-based\n* [Application Makefile](https://stnolting.github.io/neorv32/#_application_makefile) - turning _your_ application into an executable\n* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader\n* [Image Generator](https://stnolting.github.io/neorv32/#_executable_image_formats) - create (FPGA) memory initialization files from your application\n* [Semihosting](https://stnolting.github.io/neorv32/#_semihosting) - access files and system services on the host computer\n\n### :rocket: [User Guide](https://stnolting.github.io/neorv32/ug/) - Getting Started\n\n* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup) - install and set up the RISC-V GCC toolchain\n* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - set up a new NEORV32 FPGA project\n* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware\n* [Convert to Verilog](https://stnolting.github.io/neorv32/ug/#_neorv32_in_verilog) - turn the NEORV32 into an all-Verilog design\n* [Package as Vivado IP block](https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block) - turn the entire processor into an interactive AMD Vivado IP block\n* [Using Eclipse](https://stnolting.github.io/neorv32/ug/#_eclipse_ide) - use the Eclipse IDE for developing and debugging\n\nThis is an open-source project that is free of charge and provided under an\npermissive [license](https://github.com/stnolting/neorv32/blob/main/LICENSE).\nSee the [legal](https://stnolting.github.io/neorv32/#_legal) section for more information.\n\n\n## Contributing\n\nContributions are very welcome! If you’d like to improve something, fix a bug, or add a feature,\nfeel free to open an issue or submit a pull request. See how to [contribute](CONTRIBUTING.md).\nA big **thank you** goes out to the community and all contributors who help improve this project:\n\n\u003ca href=\"https://github.com/stnolting/neorv32/graphs/contributors\"\u003e\n  \u003cimg src=\"https://contrib.rocks/image?repo=stnolting/neorv32\" /\u003e\n\u003c/a\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fstnolting%2Fneorv32","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fstnolting%2Fneorv32","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fstnolting%2Fneorv32/lists"}