{"id":13648141,"url":"https://github.com/stnolting/neorv32-riscof","last_synced_at":"2025-07-30T16:04:29.407Z","repository":{"id":61655529,"uuid":"538214812","full_name":"stnolting/neorv32-riscof","owner":"stnolting","description":"✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.","archived":false,"fork":false,"pushed_at":"2025-07-28T17:50:04.000Z","size":16405,"stargazers_count":34,"open_issues_count":2,"forks_count":8,"subscribers_count":5,"default_branch":"main","last_synced_at":"2025-07-28T19:32:26.294Z","etag":null,"topics":["ghdl","isa","neorv32","processor","risc-v","riscof","riscv","sail-riscv","verification","vhdl"],"latest_commit_sha":null,"homepage":"https://github.com/stnolting/neorv32","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/stnolting.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2022-09-18T19:13:41.000Z","updated_at":"2025-07-28T17:50:08.000Z","dependencies_parsed_at":"2023-12-21T10:23:08.823Z","dependency_job_id":"f88b7f83-f1ee-4e29-97b3-0f324cad27cb","html_url":"https://github.com/stnolting/neorv32-riscof","commit_stats":null,"previous_names":[],"tags_count":0,"template":true,"template_full_name":null,"purl":"pkg:github/stnolting/neorv32-riscof","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-riscof","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-riscof/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-riscof/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-riscof/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/stnolting","download_url":"https://codeload.github.com/stnolting/neorv32-riscof/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-riscof/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":267895235,"owners_count":24162163,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-07-30T02:00:09.044Z","response_time":70,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["ghdl","isa","neorv32","processor","risc-v","riscof","riscv","sail-riscv","verification","vhdl"],"created_at":"2024-08-02T01:04:00.048Z","updated_at":"2025-07-30T16:04:29.396Z","avatar_url":"https://github.com/stnolting.png","language":"Python","funding_links":[],"categories":["Python"],"sub_categories":[],"readme":"# NEORV32 Core Verification using RISCOF\n\n[![neorv32-riscof](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-riscof/main.yml?branch=main\u0026longCache=true\u0026style=flat-square\u0026label=neorv32-riscof\u0026logo=Github%20Actions\u0026logoColor=fff)](https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml)\n[![License](https://img.shields.io/github/license/stnolting/neorv32-riscof?longCache=true\u0026style=flat-square\u0026label=License)](https://github.com/stnolting/neorv32-riscof/blob/main/LICENSE)\n\n1. [Prerequisites](#prerequisites)\n2. [Setup Configuration](#setup-configuration)\n3. [Device-Under-Test (DUT)](#device-under-test-dut)\n\nThis repository is a port of the \"**RISCOF** RISC-V Architectural Test Framework\" to test the\n[NEORV32 RISC-V Processor](https://github.com/stnolting/neorv32) for compatibility to the RISC-V\nuser and privileged ISA specifications. **Sail RISC-V** is used as reference model.\nCurrently, the following tests are supported:\n\n- [x] `rv32i_m\\A` - atomic memory operations (`Zaamo` only)\n- [x] `rv32i_m\\B` - bit-manipulation (`Zba` + `Zbb` + `Zbs`)\n- [x] `rv32i_m\\C` - compressed instructions (`Zca` + `Zcb`)\n- [x] `rv32i_m\\I` - base integer ISA\n- [x] `rv32i_m\\K` - scalar cryptography, `Zkn` and `Zks` (`Zbkb` + `Zbkc` + `Zbkx` + `Zknd` + `Zkne` + `Zknh` + `Zksed` + `Zksh`)\n- [x] `rv32i_m\\M` - hardware integer multiplication and division\n- [x] `rv32i_m\\Zicond` - conditional operations\n- [x] `rv32i_m\\Zifencei` - instruction stream synchronization\n- [x] `rv32i_m\\privilege` - privileged machine-mode architecture\n\n\u003e [!TIP]\n\u003e The general structure of this repository was setup according to the\n[RISCOF installation guide](https://riscof.readthedocs.io/en/stable/installation.html).\n\n\n## Prerequisites\n\nSeveral tools and submodules are required to run this port of the architecture test framework. The repository's\nGitHub [Actions workflow](https://github.com/stnolting/neorv32-riscof/blob/main/.github/workflows/main.yml)\ntakes care of installing all the required packages.\n\n* [neorv32](https://github.com/stnolting/neorv32) submodule - the device under test (DUT)\n* [riscv-arch-test](https://github.com/riscv-non-isa/riscv-arch-test) submodule - architecture test cases\n* [RISC-V GCC toolchain](https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack) - for compiling native `rv32` code\n* [Sail RISC-V](https://github.com/riscv/sail-riscv) - the reference model (a pre-built binary can be found in\nthe [`bin`](https://github.com/stnolting/neorv32-riscof/tree/main/bin) folder)\n* [RISCOF](https://github.com/riscv-software-src/riscof) - the architecture test framework (including\n[riscv-isac](https://github.com/riscv-software-src/riscv-isac) and [riscv-config](https://github.com/riscv-software-src/riscv-config))\n* [GHDL](https://github.com/ghdl/ghdl) - the _awesome_ VHDL simulator for simulating the DUT\n\n\u003e [!IMPORTANT]\n\u003e The `riscv-arch-test` submodule is pinned to a specific commit and ignored by _dependabot_. The source repository\nis under continuous development. Unfortunately, sometimes non-compatible modifications (i.e. test cases that forget\nto check for actually configured ISA extensions; see https://github.com/riscv-non-isa/riscv-arch-test/issues/552)\nsneak into the main branch.\n\nThe framework (running all tests) is invoked via a single shell script\n[`run.sh`](https://github.com/stnolting/neorv32-riscof/blob/main/run.sh) that returns 0 if all tests were executed\nsuccessfully or 1 if there were any errors. The exit code of this script is used to determine the overall success\nof the GitHub Actions workflow.\n\n\n## Setup Configuration\n\nThe RISCOF [config.ini](https://github.com/stnolting/neorv32-riscof/blob/main/config.ini) file is used to configure\nthe plugins to be used: the device-under-test (\"DUT\") and the reference model (\"REF\"). The ISA, debug and platform\nspecifications, which define target-specific configurations like available ISA extensions, ISA spec. versions and\nplatform modules (like MTIME), are defined by `YAML` files in the according plugin folders.\n\n* DUT: `neorv32` in [`plugin-neorv32`](https://github.com/stnolting/neorv32-riscof/tree/main/plugin-neorv32)\n* REF: `sail_cSim` in [`plugin-sail_cSim`](https://github.com/stnolting/neorv32-riscof/tree/main/plugin-sail_cSim)\n\nEach plugin folder also provides low-level _environment_ files like linker scripts (to generate an executable\nimage matching the target's memory layout) as well as platform-specific code (for example to initialize the target\nand to dump the final test signatures/results).\n\nThe official [RISC-V architecture tests](https://github.com/riscv-non-isa/riscv-arch-test) repository provides the\nindividual test cases for all (ratified) RISC-V ISA extensions (user and privilege ISA) that are currently supported\nby the DUT. Each test case checks a single instruction or core feature and is compiled into a plugin-specific\nexecutable using a [prebuilt RISC-V GCC toolchain](https://github.com/stnolting/riscv-gcc-prebuilt).\n\nThe \"golden reference\" data is generated by the **Sail RISC-V Model**. This data is compared against the results of\nthe DUT. The final test report is made available as CSS-flavored HTML file via the\n[GitHib actions artifact](https://github.com/stnolting/neorv32-riscof/actions).\n\n\n## Device-Under-Test (DUT)\n\nThe [`sim`](https://github.com/stnolting/neorv32-riscof/tree/main/sim) folder provides a plain-VHDL testbench\nand shell scripts to simulate the NEORV32 processor using **GHDL**. The testbench provides generics to configure the\nDUT's RISC-V ISA extensions and also to pass a plain ASCII HEX file, which represents the _memory image_ containing\nthe actual executable. This file generated from a test-case-specific ELF file. The makefile in the `sim` folder\ntakes care of compilation and will also convert the final memory image into a plain HEX file. Note that this makefile\nuses the default software framework from the NEORV32 submodule.\n\nThe testbench implements a CPU-external memory module that get initialized with the actual memory image generated by the\ntest framework. This memory is attached to the processor via its external Wishbone bus interface and is mapped to the core's\nreset address at `0x00000000`. The memory is implemented as 4 individual byte-wide memories each providing 1/4 of the total\nmemory size. This \"splitting\" is required as GHDL has problems handling large objects (see https://github.com/ghdl/ghdl/issues/1592).\n\nThe final test result data (= test signature) is written to a file (`DUT-neorv32.signature`) by the testbench via\nconsecutive write accesses to address `0xF0000004`. The testbench also provides several memory-mapped \"triggers\" (at\naddress `0xF0000000`) to quit the current simulation using VHDL08's `finish` statement or to trigger CPU-external\nRISC-V machine-level interrupts (MTI: machine timer interrupt; MEI: machine external interrupt; MSI: machine software\ninterrupt).\n\nThe simulation scripts and the makefile for generating the memory initialization file are invoked and orchestrated from\na DUT-specific Python script in the DUT's plugin folder\n(-\u003e [`plugin-neorv32/riscof_neorv32.py`](https://github.com/stnolting/neorv32-riscof/blob/main/plugin-neorv32/riscof_neorv32.py)).\nThis Python script makes extensive use of shell commands to move and execute files and scripts.\n\n\u003e [!IMPORTANT]\n\u003e The Python scripts of **both plugins** override the default `SET_REL_TVAL_MSK` macro from\n`riscv-arch-test/riscv-test-suite/env/arch_test.h` to remove the BREAK exception cause from the relocation list as the\nNEORV32 sets `mtval` to zero for this type of exception. This is **explicitly permitted** by the RISC-V priv. spec.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fstnolting%2Fneorv32-riscof","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fstnolting%2Fneorv32-riscof","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fstnolting%2Fneorv32-riscof/lists"}