{"id":28124601,"url":"https://github.com/stnolting/neorv32-setups","last_synced_at":"2026-01-25T07:37:20.772Z","repository":{"id":36956827,"uuid":"446662760","full_name":"stnolting/neorv32-setups","owner":"stnolting","description":"📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.","archived":false,"fork":false,"pushed_at":"2026-01-11T11:54:52.000Z","size":950,"stargazers_count":86,"open_issues_count":1,"forks_count":37,"subscribers_count":8,"default_branch":"main","last_synced_at":"2026-01-11T16:05:39.980Z","etag":null,"topics":["fpga","ghdl","intel","lattice","neorv32","risc-v","soc","verilog","vhdl","xilinx","yosys"],"latest_commit_sha":null,"homepage":"https://github.com/stnolting/neorv32","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/stnolting.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":"CODE_OF_CONDUCT.md","threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2022-01-11T03:20:30.000Z","updated_at":"2026-01-11T11:54:56.000Z","dependencies_parsed_at":"2023-10-05T01:39:26.259Z","dependency_job_id":"959b857c-0c26-469f-bf02-9ced2a01ff64","html_url":"https://github.com/stnolting/neorv32-setups","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/stnolting/neorv32-setups","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-setups","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-setups/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-setups/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-setups/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/stnolting","download_url":"https://codeload.github.com/stnolting/neorv32-setups/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-setups/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28747709,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-25T05:12:38.112Z","status":"ssl_error","status_checked_at":"2026-01-25T05:04:50.338Z","response_time":113,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","ghdl","intel","lattice","neorv32","risc-v","soc","verilog","vhdl","xilinx","yosys"],"created_at":"2025-05-14T09:18:39.230Z","updated_at":"2026-01-25T07:37:20.765Z","avatar_url":"https://github.com/stnolting.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Exemplary NEORV32 Setups and Projects\n\n[![Containers](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-setups/Containers.yml?branch=main\u0026longCache=true\u0026style=flat-square\u0026label=Containers\u0026logo=Github%20Actions\u0026logoColor=fff)](https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AContainers)\n[![Implementation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32-setups/Implementation.yml?branch=main\u0026longCache=true\u0026style=flat-square\u0026label=Implementation\u0026logo=Github%20Actions\u0026logoColor=fff)](https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation)\n[![License](https://img.shields.io/github/license/stnolting/neorv32-setups?longCache=true\u0026style=flat-square\u0026label=License)](https://github.com/stnolting/neorv32-setups/blob/main/LICENSE)\n\n* [**Community Projects** (hardware / software)](#community-projects)\n* [**Setups using Commercial Toolchains** (FPGA setups)](#setups-using-commercial-toolchains)\n* [**Setups using Open-Source Toolchains** (FPGA setups)](#setups-using-open-source-toolchains)\n* [Adding Your Project or Setup](#ADDING-YOUR-PROJECT-OR-SETUp)\n* [Setup-Specific NEORV32 Software Framework Modifications](#setup-specific-neorv32-software-framework-modifications)\n\nThis repository provides community projects as well as exemplary setups for different FPGAs, platforms, boards\nand toolchains for the [**NEORV32 RISC-V Processor**](https://github.com/stnolting/neorv32).\nProject maintainers may make pull requests against this repository to add or link their setups and projects.\n\n\u003e [!TIP]\n\u003e **Ready-to-use bitstreams** for the provided _open source toolchain-based setups_ are available via the assets of the[Implementation Workflow](https://github.com/stnolting/neorv32-setups/actions/workflows/Implementation.yml).\n\n\n## Community Projects\n\nThis list shows projects that focus on custom hard- or software modifications, specific applications, etc.\n\n| Link | Description | Author(s) |\n|:-----|:------------|:----------|\n| :earth_africa: [github.com/motius](https://github.com/motius/neorv32/tree/add-custom-crc32-module) | **tutorial:** custom CRC32 processor module for the nexys-a7 boards | [motius](https://github.com/motius) ([ikstvn](https://github.com/ikstvn), [turbinenreiter](https://github.com/turbinenreiter)) |\n| :earth_africa: [neorv32-examples](https://github.com/emb4fun/neorv32-examples) | NEORV32 setups/projects for different Intel/Terasic boards | [emb4fun](https://github.com/emb4fun) |\n| :earth_africa: [neorv32-xmodem-bootloader](https://www.emb4fun.de/riscv/neorv32xboot/index.html) | A XModem Bootloader for the DE0-Nano board | [emb4fun](https://github.com/emb4fun) |\n| :earth_africa: [neorv32-xip-bootloader](https://github.com/betocool-prog/neorv32-xip-bootloader) | A XIP (eXecute In Place) Bootloader for the NEORV32| [betocool-prog](https://github.com/betocool-prog) |\n\n\n## Setups using Commercial Toolchains\n\nThe setups using commercial toolchains provide pre-configured project files that can be opened with the according FPGA tools.\n\n| Setup | Toolchain | Board | FPGA | Author(s) |\n|:------|:----------|:------|:-----|:----------|\n| :file_folder: [`de0-nano-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/quartus/de0-nano-test-setup) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English\u0026CategoryNo=139\u0026No=593)                     | Intel Cyclone IV `EP4CE22F17C6N`          | [stnolting](https://github.com/stnolting) |\n| :file_folder: [`de10-nano-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/quartus/de10-nano-test-setup) | Intel Quartus Prime | [Terasic DE10-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English\u0026CategoryNo=167\u0026No=1046#contents)                     | Intel Cyclone V `5CSEBA6U23I7`          | [provoostkris](https://github.com/provoostkris) |\n| :file_folder: [`de0-nano-test-setup-qsys`](quartus/de0-nano-test-setup-qsys) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English\u0026CategoryNo=139\u0026No=593)                     | Intel Cyclone IV `EP4CE22F17C6N`          | [torerams](https://github.com/torerams) |\n| :file_folder: [`de0-nano-test-setup-avalonmm`](quartus/de0-nano-test-setup-avalonmm-wrapper) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English\u0026CategoryNo=139\u0026No=593)                     | Intel Cyclone IV `EP4CE22F17C6N`          | [torerams](https://github.com/torerams) |\n| :file_folder: [`terasic-cyclone-V-gx-starter-kit-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/quartus/terasic-cyclone-V-gx-starter-kit-test-setup) | Intel Quartus Prime | [Terasic Cyclone-V GX Starter Kit](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English\u0026CategoryNo=167\u0026No=830) | Intel Cyclone V `5CGXFC5C6F27C7N` | zs6mue |\n| :file_folder: [`UPduino_v3`](https://github.com/stnolting/neorv32-setups/tree/main/radiant/UPduino_v3)                   | Lattice Radiant     | [tinyVision.ai Inc. UPduino `v3.0`](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [stnolting](https://github.com/stnolting) |\n| :file_folder: [`iCEBreaker`](https://github.com/stnolting/neorv32-setups/tree/main/radiant/iCEBreaker)                   | Lattice Radiant     | [iCEBreaker @ GitHub](https://github.com/icebreaker-fpga/icebreaker)                                                              | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [stnolting](https://github.com/stnolting) |\n| :file_folder: [`arty-a7-35-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/arty-a7-test-setup) | Xilinx Vivado       | [Digilent Arty A7-35](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start)                               | Xilinx Artix-7 `XC7A35TICSG324-1L`        | [stnolting](https://github.com/stnolting) |\n| :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/nexys-a7-test-setup)  | Xilinx Vivado       | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start)                                | Xilinx Artix-7 `XC7A50TCSG324-1`          | [AWenzel83](https://github.com/AWenzel83) |\n| :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/nexys-a7-test-setup)  | Xilinx Vivado       | [Digilent Nexys 4 DDR](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start)                          | Xilinx Artix-7 `XC7A100TCSG324-1`         | [AWenzel83](https://github.com/AWenzel83) |\n| :file_folder: [`z7-nano-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/z7-nano-test-setup)  | Xilinx Vivado       | [Microphase Z7 Nano FPGA Board](https://github.com/MicroPhase/fpga-docs/blob/master/schematic/Z7-NANO_R21.pdf)                              | Xilinx ZynQ 7000 `c7z020clg400-2`        | [provoostkris](https://github.com/provoostkris) |\n| :file_folder: [`cora-z7-test-setup`](https://github.com/stnolting/neorv32-setups/tree/main/vivado/cora-z7-test-setup)  | Xilinx Vivado       | [Digilent Cora Z7](https://digilent.com/reference/programmable-logic/cora-z7/start)                              | Xilinx ZynQ 7000 `xc7z007sclg400-1`        | [eivindbergem](https://github.com/eivindbergem) |\n| :file_folder: [`on-chip-debugger-intel`](https://github.com/stnolting/neorv32-setups/tree/main/quartus/on-chip-debugger-intel) | Intel Quartus Prime | [Gecko4Education](https://gecko-wiki.ti.bfh.ch/gecko4education:start)                                                       | Intel Cyclone IV E `EP4CE15F23C8`         | [NikLeberg](https://github.com/NikLeberg) |\n| :file_folder: [`tang-nano-9k`](https://github.com/stnolting/neorv32-setups/tree/main/gowineda/tang-nano-9k)              | Gowin EDA           | [Sipeed Tang Nano 9K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html)                                         | Gowin LittleBee GW1NR-9 `GW1NR-LV9QN88PC6/I5` | [IvanVeloz](https://github.com/IvanVeloz)\n| :file_folder: [`tang-nano-20k`](https://github.com/stnolting/neorv32-setups/tree/main/gowineda/tang-nano-20k)              | Gowin EDA           | [Sipeed Tang Nano 20K](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html)                                         | Gowin Morningside GW2A-18 `GW2AR-LV18QN88C8/I7` | [duvitech-llc](https://github.com/duvitech-llc)\n\n\n## Setups using Open-Source Toolchains\n\nMost OSS setups using open-source toolchains are located in the\n[`osflow`](https://github.com/stnolting/neorv32-setups/tree/main/osflow) folder.\nSee the [README](https://github.com/stnolting/neorv32-setups/blob/main/osflow/README.md)\nthere for more information how to run a specific setup and how to add new targets.\n\n| Setup | Toolchain | Board | FPGA | Author(s) |\n|:------|:----------|:------|:-----|:----------|\n| :file_folder: [`UPDuino-v3.0`](https://github.com/stnolting/neorv32-setups/tree/main/osflow) | GHDL, Yosys, nextPNR | [UPduino v3.0](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [tmeissner](https://github.com/tmeissner) |\n| :file_folder: [`FOMU`](https://github.com/stnolting/neorv32-setups/tree/main/osflow)        | GHDL, Yosys, nextPNR | [FOMU](https://tomu.im/fomu.html)                                                                             | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [umarcor](https://github.com/umarcor) |\n| :file_folder: [`iCESugar`](https://github.com/stnolting/neorv32-setups/tree/main/osflow)    | GHDL, Yosys, nextPNR | [iCESugar](https://github.com/wuxx/icesugar/blob/master/README_en.md)                                         | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [umarcor](https://github.com/umarcor) |\n| :file_folder: [`AlhambraII`](https://github.com/stnolting/neorv32-setups/tree/main/osflow)  | GHDL, Yosys, nextPNR | [AlhambraII](https://alhambrabits.com/alhambra/)                                                              | Lattice iCE40HX4K                         | [zipotron](https://github.com/zipotron) |\n| :file_folder: [`Orange Crab`](https://github.com/stnolting/neorv32-setups/tree/main/osflow) | GHDL, Yosys, nextPNR | [Orange Crab](https://github.com/gregdavill/OrangeCrab)                                                       | Lattice ECP5-25F                          | [umarcor](https://github.com/umarcor), [jeremyherbert](https://github.com/jeremyherbert) |\n| :file_folder: [`ULX3S`](https://github.com/stnolting/neorv32-setups/tree/main/osflow)       | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/)                                                                           | Lattice ECP5 `LFE5U-85F-6BG381C`          | [zipotron](https://github.com/zipotron) |\n| :file_folder: [`GateMateA1-EVB`](https://github.com/stnolting/neorv32-setups/tree/main/cologne_chip/GateMateA1-EVB) | GHDL, Yosys, CC P_R | [GateMateA1-EVB(-2M)](https://www.olimex.com/Products/FPGA/GateMate/GateMateA1-EVB/)             | Cologne Chip GateMate `CCGM1A1`           | [stnolting](https://github.com/stnolting) |\n| :file_folder: ChipWhisperer [`iCE40CW312`](https://github.com/stnolting/neorv32-setups/tree/main/osflow) | GHDL, Yosys, nextPNR | [CW312T_ICE40UP](https://github.com/newaetech/chipwhisperer-target-cw308t/tree/main/CW312T_ICE40UP) | Lattice iCE40 UltraPlus `iCE40UP5K-UWG30` | [colinoflynn](https://github.com/colinoflynn) |\n| :earth_africa: [`ULX3S-SDRAM`](https://github.com/zipotron/neorv32-complex-setups)          | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/)                                                                           | Lattice ECP5 `LFE5U-85F-6BG381C`          | [zipotron](https://github.com/zipotron) |\n| :file_folder: [`TangNano20k`](https://github.com/stnolting/neorv32-setups/tree/main/osflow) | GHDL, Yosys, nextPNR | [Tang Nano 20K](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html)                         | GOWIN GW2AR `GW2AR-18 QN88`          | [d-orthofer](https://github.com/d-orthofer) |\n\n\n------------------------------------------------------\n\n\n### Adding Your Project or Setup\n\nPlease respect the following guidelines if you'd like to add or link your setup/project to the list:\n\n* check out the project's [code of conduct](https://github.com/stnolting/neorv32-setups/tree/master/CODE_OF_CONDUCT.md)\n* for FPGA- / board- / toolchain-specific **setups**:\n  * a \"setup\" is a wrapped (and maybe script-aided) implementation of the NEORV32 processor for a certain FPGA/board/toolchain\n  * add a link if the board you are using provides online documentation or can be purchased somewhere\n  * use the :file_folder: emoji (`:file_folder:`) if the setup is located in this repository; use the :earth_africa:\nemoji (`:earth_africa:`) if it is a link to your local project\n  * please add a `README.md` file to give some brief information about the setup and a `.gitignore` file to keep things clean\n  * for local setups you can add your setup to the [implementation](https://github.com/stnolting/neorv32-setups/blob/main/.github/generate-job-matrix.py)\nGitHub actions workflow to automatically generate up-to-date bitstreams for your setup\n* for **projects**:\n  * provide a link to your project (use the :earth_africa: (`:earth_africa:`) emoji)\n  * provide a short description\n  * further information should be provided by a project-local README\n\n\n### Setup-Specific NEORV32 Software Framework Modifications\n\nIn order to use the features provided by the setups, minor *optional* changes can be made to the default NEORV32 setup.\n\n* To change the default data memory size take a look at the User Guide section\n[_General Software Framework Setup_](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup)\n* To modify the SPI flash base address for storing/booting software application see User Guide section\n[_Customizing the Internal Bootloader_](https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fstnolting%2Fneorv32-setups","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fstnolting%2Fneorv32-setups","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fstnolting%2Fneorv32-setups/lists"}